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The attached patches provides part 7 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
#ifndef XTENSA_COREBITS_H
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#define XTENSA_COREBITS_H
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/*
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* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
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*
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* xtensa/corebits.h - Xtensa Special Register field positions and masks.
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*
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* (In previous releases, these were defined in specreg.h, a generated file.
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* This file is not generated, i.e. it is processor configuration independent.)
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*/
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/* EXCCAUSE register fields: */
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#define EXCCAUSE_EXCCAUSE_SHIFT 0
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#define EXCCAUSE_EXCCAUSE_MASK 0x3F
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/* Exception causes (mostly incomplete!): */
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#define EXCCAUSE_ILLEGAL 0
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#define EXCCAUSE_SYSCALL 1
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#define EXCCAUSE_IFETCHERROR 2
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#define EXCCAUSE_LOADSTOREERROR 3
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#define EXCCAUSE_LEVEL1INTERRUPT 4
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#define EXCCAUSE_ALLOCA 5
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/* PS register fields: */
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#define PS_WOE_SHIFT 18
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#define PS_WOE_MASK 0x00040000
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#define PS_WOE PS_WOE_MASK
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_MASK 0x00030000
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#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
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#define PS_OWB_SHIFT 8
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#define PS_OWB_MASK 0x00000F00
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#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
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#define PS_RING_SHIFT 6
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#define PS_RING_MASK 0x000000C0
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#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
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#define PS_UM_SHIFT 5
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#define PS_UM_MASK 0x00000020
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#define PS_UM PS_UM_MASK
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#define PS_EXCM_SHIFT 4
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#define PS_EXCM_MASK 0x00000010
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#define PS_EXCM PS_EXCM_MASK
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#define PS_INTLEVEL_SHIFT 0
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#define PS_INTLEVEL_MASK 0x0000000F
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#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
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/* Backward compatibility (deprecated): */
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#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
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#define PS_PROGSTACK_MASK PS_UM_MASK
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#define PS_PROG_SHIFT PS_UM_SHIFT
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#define PS_PROG_MASK PS_UM_MASK
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#define PS_PROG PS_UM
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/* DBREAKCn register fields: */
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#define DBREAKC_MASK_SHIFT 0
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#define DBREAKC_MASK_MASK 0x0000003F
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#define DBREAKC_LOADBREAK_SHIFT 30
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#define DBREAKC_LOADBREAK_MASK 0x40000000
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#define DBREAKC_STOREBREAK_SHIFT 31
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#define DBREAKC_STOREBREAK_MASK 0x80000000
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/* DEBUGCAUSE register fields: */
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#define DEBUGCAUSE_DEBUGINT_SHIFT 5
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#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
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#define DEBUGCAUSE_BREAKN_SHIFT 4
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#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
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#define DEBUGCAUSE_BREAK_SHIFT 3
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#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
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#define DEBUGCAUSE_DBREAK_SHIFT 2
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#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
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#define DEBUGCAUSE_IBREAK_SHIFT 1
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#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
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#define DEBUGCAUSE_ICOUNT_SHIFT 0
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#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
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#endif /*XTENSA_COREBITS_H*/
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