linux/drivers/clk/zynq
Shubhrajyoti Datta a6aa462c3e clk: zynq: Update the parameters to zynq_clk_register_periph_clk
In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-29 10:17:49 -07:00
..
clkc.c clk: zynq: Update the parameters to zynq_clk_register_periph_clk 2022-03-29 10:17:49 -07:00
Makefile treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21 10:50:46 +02:00
pll.c clk: zynq: pll: Fix kernel-doc warnings 2021-12-02 17:27:24 -08:00