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The Ralink RT3883 SoCs have a built-in PCI Host Controller device. The patch adds a platform driver and device tree binding documentation for that. The patch also enables the HW_HAS_PCI config option. This is required in order to be able to enable the PCI support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
191 lines
4.7 KiB
Plaintext
191 lines
4.7 KiB
Plaintext
* Mediatek/Ralink RT3883 PCI controller
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1) Main node
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Required properties:
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- compatible: must be "ralink,rt3883-pci"
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- reg: specifies the physical base address of the controller and
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the length of the memory mapped region.
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 1.
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- #size-cells: specifies the number of cells used to represent the size
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of an address. The value must be 1.
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- ranges: specifies the translation between child address space and parent
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address space
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Optional properties:
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- status: indicates the operational status of the device.
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Value must be either "disabled" or "okay".
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2) Child nodes
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The main node must have two child nodes which describes the built-in
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interrupt controller and the PCI host bridge.
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a) Interrupt controller:
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Required properties:
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- interrupt-controller: identifies the node as an interrupt controller
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0. As such, 'interrupt-map' nodes do not
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have to specify a parent unit address.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-parent: the phandle for the interrupt controller that
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services interrupts for this device.
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends on the
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parent interrupt controller.
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b) PCI host bridge:
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Required properties:
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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- #size-cells: specifies the number of cells used to represent the size
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of an address. The value must be 2.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- device_type: must be "pci"
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- bus-range: PCI bus numbers covered
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- ranges: specifies the ranges for the PCI memory and I/O regions
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- interrupt-map-mask,
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- interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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The PCI host bridge node migh have additional sub-nodes representing
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the onboard PCI devices/PCI slots. Each such sub-node must have the
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following mandatory properties:
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- reg: used only for interrupt mapping, so only the first four bytes
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are used to refer to the correct bus number and device number.
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- device_type: must be "pci"
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If a given sub-node represents a PCI bridge it must have following
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mandatory properties as well:
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- #address-cells: must be set to <3>
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- #size-cells: must set to <2>
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- #interrupt-cells: must be set to <1>
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- interrupt-map-mask,
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- interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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Besides the required properties the sub-nodes may have these optional
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properties:
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- status: indicates the operational status of the sub-node.
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Value must be either "disabled" or "okay".
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3) Example:
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a) SoC specific dtsi file:
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pci@10140000 {
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compatible = "ralink,rt3883-pci";
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reg = <0x10140000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges; /* direct mapping */
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status = "disabled";
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pciintc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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};
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host-bridge {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 17 */
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0x8800 0 0 1 &pciintc 18
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0x8800 0 0 2 &pciintc 18
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0x8800 0 0 3 &pciintc 18
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0x8800 0 0 4 &pciintc 18
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/* IDSEL 18 */
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0x9000 0 0 1 &pciintc 19
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0x9000 0 0 2 &pciintc 19
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0x9000 0 0 3 &pciintc 19
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0x9000 0 0 4 &pciintc 19
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>;
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pci-bridge@1 {
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reg = <0x0800 0 0 0 0>;
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device_type = "pci";
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#interrupt-cells = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0x0 0 0 0>;
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interrupt-map = <0x0 0 0 0 &pciintc 20>;
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status = "disabled";
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};
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pci-slot@17 {
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reg = <0x8800 0 0 0 0>;
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device_type = "pci";
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status = "disabled";
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};
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pci-slot@18 {
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reg = <0x9000 0 0 0 0>;
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device_type = "pci";
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status = "disabled";
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};
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};
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};
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b) Board specific dts file:
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pci@10140000 {
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status = "okay";
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host-bridge {
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pci-bridge@1 {
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status = "okay";
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};
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};
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};
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