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207918461e
For more control over which functions are called with the MMU off or with the UEFI 1:1 mapping active, annotate some assembler routines as position independent. This is done by introducing ENDPIPROC(), which replaces the ENDPROC() declaration of those routines. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
127 lines
3.4 KiB
ArmAsm
127 lines
3.4 KiB
ArmAsm
/*
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* Copyright (C) 2013 ARM Ltd.
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* Copyright (C) 2013 Linaro.
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*
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* This code is based on glibc cortex strings work originally authored by Linaro
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* and re-licensed under GPLv2 for the Linux kernel. The original code can
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* be found @
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*
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* http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/
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* files/head:/src/aarch64/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* calculate the length of a string
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*
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* Parameters:
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* x0 - const string pointer
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* Returns:
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* x0 - the return length of specific string
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*/
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/* Arguments and results. */
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srcin .req x0
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len .req x0
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/* Locals and temporaries. */
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src .req x1
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data1 .req x2
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data2 .req x3
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data2a .req x4
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has_nul1 .req x5
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has_nul2 .req x6
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tmp1 .req x7
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tmp2 .req x8
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tmp3 .req x9
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tmp4 .req x10
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zeroones .req x11
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pos .req x12
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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ENTRY(strlen)
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mov zeroones, #REP8_01
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bic src, srcin, #15
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ands tmp1, srcin, #15
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b.ne .Lmisaligned
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/*
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* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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* (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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* can be done in parallel across the entire word.
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*/
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/*
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* The inner loop deals with two Dwords at a time. This has a
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* slightly higher start-up cost, but we should win quite quickly,
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* especially on cores with a high number of issue slots per
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* cycle, as we get much better parallelism out of the operations.
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*/
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.Lloop:
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ldp data1, data2, [src], #16
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.Lrealigned:
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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bic has_nul1, tmp1, tmp2
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bics has_nul2, tmp3, tmp4
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ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */
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b.eq .Lloop
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sub len, src, srcin
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cbz has_nul1, .Lnul_in_data2
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CPU_BE( mov data2, data1 ) /*prepare data to re-calculate the syndrome*/
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sub len, len, #8
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mov has_nul2, has_nul1
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.Lnul_in_data2:
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/*
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* For big-endian, carry propagation (if the final byte in the
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* string is 0x01) means we cannot use has_nul directly. The
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* easiest way to get the correct byte is to byte-swap the data
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* and calculate the syndrome a second time.
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*/
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CPU_BE( rev data2, data2 )
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CPU_BE( sub tmp1, data2, zeroones )
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CPU_BE( orr tmp2, data2, #REP8_7f )
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CPU_BE( bic has_nul2, tmp1, tmp2 )
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sub len, len, #8
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rev has_nul2, has_nul2
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clz pos, has_nul2
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add len, len, pos, lsr #3 /* Bits to bytes. */
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ret
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.Lmisaligned:
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cmp tmp1, #8
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neg tmp1, tmp1
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ldp data1, data2, [src], #16
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lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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mov tmp2, #~0
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/* Big-endian. Early bytes are at MSB. */
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CPU_BE( lsl tmp2, tmp2, tmp1 ) /* Shift (tmp1 & 63). */
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/* Little-endian. Early bytes are at LSB. */
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CPU_LE( lsr tmp2, tmp2, tmp1 ) /* Shift (tmp1 & 63). */
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orr data1, data1, tmp2
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orr data2a, data2, tmp2
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csinv data1, data1, xzr, le
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csel data2, data2, data2a, le
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b .Lrealigned
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ENDPIPROC(strlen)
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