linux/drivers/reset
Linus Torvalds bdc753c7fc Here's the main clk pull request for this merge window. We have some
late breaking reports that a patch series to rework clk rate range
 support broke boot on some devices, so I've left that branch out of this
 PR. Hopefully we can get to that next week, or punt on it and let it
 bake another cycle. That means we don't really have any changes to the
 core framework this time around besides a few typo fixes. Instead this
 is all clk driver updates and fixes.
 
 The usual suspects are here (again), with Qualcomm dominating the
 diffstat. We look to have gained support for quite a few new Qualcomm
 SoCs and Dmitry worked on updating many of the existing Qualcomm drivers
 to use clk_parent_data. After that we have MediaTek drivers getting some
 much needed updates, in particular to support GPU DVFS. There are also
 quite a few Samsung clk driver patches, but that's mostly because there
 was a maintainer change and so last release we missed some of those
 patches.
 
 Overall things look normal, but I'm slowly reviewing core framework code
 nowadays and that shows given the rate range patches had to be yanked
 last minute. Let's hope this situation changes soon.
 
 New Drivers:
  - Support for Renesas VersaClock7 clock generator family
  - Add Spreadtrum UMS512 SoC clk support
  - New clock drivers for MediaTek Helio X10 MT6795
  - Display clks for Qualcomm SM6115, SM8450
  - GPU clks for Qualcomm SC8280XP
  - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
 
 Deleted Drivers:
  - Remove DaVinci DM644x and DM646x clk driver support
 
 Updates:
  - Convert Baikal-T1 CCU driver to platform driver
  - Split reset support out of primary Baikal-T1 CCU driver
  - Add some missing clks required for RPiVid Video Decoder on RaspberryPi
  - Mark PLLC critical on bcm2835
  - More devm helpers for fixed rate registration
  - Various PXA168 clk driver fixes
  - Add resets for MediaTek MT8195 PCIe and USB
  - Miscellaneous of_node_put() fixes
  - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
  - Convert gpio-clk-gate binding to YAML
  - Various fixes to AMD/Xilinx Zynqmp clk driver
  - Graduate AMD/Xilinx "clocking wizard" driver from staging
  - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
  - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
    - Fix GPU clock topology on MT8195
    - Propogate rate changes from GPU clock gate up the tree
    - Clock mux notifiers for GPU-related PLLs
  - Conversion of more "simple" drivers to mtk_clk_simple_probe()
  - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
  - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek
  - Shrink MT8192 clock driver by deduplicating clock parent lists
  - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
    clocks for i.MX8MP
  - Drop unnecessary newline in i.MX8MM dt-bindings
  - Add more MU1 and SAI clocks dt-bindings Ids
  - Introduce slice busy bit check for i.MX93 composite clock
  - Introduce white list bit check for i.MX93 composite clock
  - Add new i.MX93 clock gate
  - Add MU1 and MU2 clocks to i.MX93 clock provider
  - Add SAI IPG clocks to i.MX93 clock provider
  - add generic clocks for U(S)ART available on SAMA5D2 SoCs
  - reset controller support for Polarfire clocks
  - .round_rate and .set rate support for clk-mpfs
  - code cleanup for clk-mpfs
  - PLL support for PolarFire SoC's Clock Conditioning Circuitry
  - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H
  - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
  - Add I2C clocks and resets on RZ/V2M
  - Document clock support for the RZ/Five SoC
  - mux-variant clock using the table variant to select parents
  - clock controller for the rv1126 soc
  - conversion of rk3128 to yaml and relicensing of the yaml bindings
    to gpl2+MIT (following dt-binding guildelines)
  - Exynos7885: add FSYS, TREX and MFC clock controllers
  - Exynos850: add IS and AUD (audio) clock controllers with bindings
  - ExynosAutov9: add FSYS clock controllers with bindings
  - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
    controllers, due to duplicated entries.  This is an acceptable ABI
    break: recently developed/added platform so without legacies, acked
    by known users/developers
  - ExynosAutov9: add few missing Peric 0/1 gates
  - ExynosAutov9: correct register offsets of few Peric 0/1 clocks
  - Minor code improvements (use of_device_get_match_data() helper, code
    style)
  - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
    already maintainers that architecture/platform
  - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention
    issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP
  - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
  - Qualcomm SDM660 SDCC1 moved to floor clk ops
  - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was
    added/fixed
  - The Qualcomm MSM8996 CPU clocks are updated with support for ACD
  - Support for Qualcomm SDM670 GCC and RPMh clks was added
  - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
    num_parents was done for many Qualcomm SoCs
  - Support for per-reset defined delay on Qualcomm was introduced
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmM/trwRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUEoA/+LiftbrF8Xtu7lGdxRjqLzRftUmHaUQWO
 d0cadtzMsgxzFJsxp99IiJBVJoaYCBOGlnZDx8p/JGv+mmdhl5+yHgKQbR8nEmTk
 5A+bdA1okOdm8SPBPMcLvuMjsgmx+DHkuxvnC2hT8ZGfQDoa+6PnObpP30LJkHT0
 oVY8g8ScEuHI5eJcNz3UgxAetKeJd+WRQPxKCrjsOeyhWuNAJ7wdTVQjjzH49X4C
 RS3fjeHvhr2VZm23IgildY++a6hPO72gtBjEpDRoFwnmWAVqUtxiwptoJJNkC5kB
 toD/ndQHOLh/XOJFKgksS20L4JHtSp5F3Ma8sIuOjAXmDCyqMdTQhydnl5Pyrow+
 ct8BMUGkx0Sw8pXBJYINtHpwTtIxvLu/sBNqBb/lRCWd8byrPlUnKvF/COcoxp27
 miZTwJI28fHU5a2K/46iWZCI5YUvVcnBSz8WbEWWvOltIT8S0JvZozA3KuRm5vys
 /k2HaQwO2I0QWQzPjfg6SRlTTWH6p+Hc47fSg7LSM6Scsb7ZraajTM2QOvgn7Mgp
 m/136q7jr9mvuLqqy1fBY3F2hDZYNSJX+UfmIFcpCyxvht0GVFN9YCc+Ibgyl2vQ
 P3b9LXV2OqhtDJg6ds7v8aPgAGUwUFO8GTPBG1cuom7z5u/kdIpjKaFAyr8wWSuJ
 wqPIFevggsA=
 =9jI+
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "We have some late breaking reports that a patch series to rework clk
  rate range support broke boot on some devices, so I've left that
  branch out of this. Hopefully we can get to that next week, or punt on
  it and let it bake another cycle. That means we don't really have any
  changes to the core framework this time around besides a few typo
  fixes. Instead this is all clk driver updates and fixes.

  The usual suspects are here (again), with Qualcomm dominating the
  diffstat. We look to have gained support for quite a few new Qualcomm
  SoCs and Dmitry worked on updating many of the existing Qualcomm
  drivers to use clk_parent_data. After that we have MediaTek drivers
  getting some much needed updates, in particular to support GPU DVFS.
  There are also quite a few Samsung clk driver patches, but that's
  mostly because there was a maintainer change and so last release we
  missed some of those patches.

  Overall things look normal, but I'm slowly reviewing core framework
  code nowadays and that shows given the rate range patches had to be
  yanked last minute. Let's hope this situation changes soon.

  New Drivers:
   - Support for Renesas VersaClock7 clock generator family
   - Add Spreadtrum UMS512 SoC clk support
   - New clock drivers for MediaTek Helio X10 MT6795
   - Display clks for Qualcomm SM6115, SM8450
   - GPU clks for Qualcomm SC8280XP
   - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers

  Deleted Drivers:
   - Remove DaVinci DM644x and DM646x clk driver support

  Updates:
   - Convert Baikal-T1 CCU driver to platform driver
   - Split reset support out of primary Baikal-T1 CCU driver
   - Add some missing clks required for RPiVid Video Decoder on
     RaspberryPi
   - Mark PLLC critical on bcm2835
   - More devm helpers for fixed rate registration
   - Various PXA168 clk driver fixes
   - Add resets for MediaTek MT8195 PCIe and USB
   - Miscellaneous of_node_put() fixes
   - Nuke dt-bindings/clk path (again) by moving headers to
     dt-bindings/clock
   - Convert gpio-clk-gate binding to YAML
   - Various fixes to AMD/Xilinx Zynqmp clk driver
   - Graduate AMD/Xilinx "clocking wizard" driver from staging
   - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
   - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
   - Fix GPU clock topology on MT8195
   - Propogate rate changes from GPU clock gate up the tree
   - Clock mux notifiers for GPU-related PLLs
   - Conversion of more "simple" drivers to mtk_clk_simple_probe()
   - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
   - Fixes to previous |struct clk| to |struct clk_hw| conversion on
     MediaTek
   - Shrink MT8192 clock driver by deduplicating clock parent lists
   - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
     clocks for i.MX8MP
   - Drop unnecessary newline in i.MX8MM dt-bindings
   - Add more MU1 and SAI clocks dt-bindings Ids
   - Introduce slice busy bit check for i.MX93 composite clock
   - Introduce white list bit check for i.MX93 composite clock
   - Add new i.MX93 clock gate
   - Add MU1 and MU2 clocks to i.MX93 clock provider
   - Add SAI IPG clocks to i.MX93 clock provider
   - add generic clocks for U(S)ART available on SAMA5D2 SoCs
   - reset controller support for Polarfire clocks
   - .round_rate and .set rate support for clk-mpfs
   - code cleanup for clk-mpfs
   - PLL support for PolarFire SoC's Clock Conditioning Circuitry
   - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
     V4H
   - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
   - Add I2C clocks and resets on RZ/V2M
   - Document clock support for the RZ/Five SoC
   - mux-variant clock using the table variant to select parents
   - clock controller for the rv1126 soc
   - conversion of rk3128 to yaml and relicensing of the yaml bindings
     to gpl2+MIT (following dt-binding guildelines)
   - Exynos7885: add FSYS, TREX and MFC clock controllers
   - Exynos850: add IS and AUD (audio) clock controllers with bindings
   - ExynosAutov9: add FSYS clock controllers with bindings
   - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
     controllers, due to duplicated entries. This is an acceptable ABI
     break: recently developed/added platform so without legacies, acked
     by known users/developers
   - ExynosAutov9: add few missing Peric 0/1 gates
   - ExynosAutov9: correct register offsets of few Peric 0/1 clocks
   - Minor code improvements (use of_device_get_match_data() helper,
     code style)
   - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
     he already maintainers that architecture/platform
   - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
     retention issues during suspend of USB on Qualcomm sc7180/sc7280
     and SC8280XP
   - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
   - Qualcomm SDM660 SDCC1 moved to floor clk ops
   - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
     was added/fixed
   - The Qualcomm MSM8996 CPU clocks are updated with support for ACD
   - Support for Qualcomm SDM670 GCC and RPMh clks was added
   - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
     num_parents was done for many Qualcomm SoCs
   - Support for per-reset defined delay on Qualcomm was introduced"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
  clk: qcom: gcc-sm6375: Ensure unsigned long type
  clk: qcom: gcc-sm6375: Remove unused variables
  clk: qcom: kpss-xcc: convert to parent data API
  clk: introduce (devm_)hw_register_mux_parent_data_table API
  clk: allow building lan966x as a module
  clk: clk-xgene: simplify if-if to if-else
  clk: ast2600: BCLK comes from EPLL
  clk: clocking-wizard: Depend on HAS_IOMEM
  clk: clocking-wizard: Use dev_err_probe() helper
  clk: nxp: fix typo in comment
  clk: pxa: add a check for the return value of kzalloc()
  clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
  dt-bindings: clock: vc5: Add 5P49V6975
  clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
  clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
  clk: Renesas versaclock7 ccf device driver
  dt-bindings: Renesas versaclock7 device tree bindings
  clk: ti: Balance of_node_get() calls for of_find_node_by_name()
  clk: imx: scu: fix memleak on platform_device_add() fails
  clk: vc5: Use regmap_{set,clear}_bits() where appropriate
  ...
2022-10-08 10:06:48 -07:00
..
hisilicon reset: hi6220: Use the correct HiSilicon copyright 2021-06-07 10:44:38 +02:00
sti reset: sti/syscfg: replace comma with semicolon 2021-05-10 09:41:43 +02:00
tegra reset: tegra-bpmp: Restore Handle errors in BPMP response 2022-04-04 11:14:13 +02:00
core.c reset: ACPI reset support 2022-05-03 17:41:25 +02:00
Kconfig Here's the main clk pull request for this merge window. We have some 2022-10-08 10:06:48 -07:00
Makefile reset: add polarfire soc reset support 2022-09-14 10:55:17 +03:00
reset-a10sr.c reset: a10sr: add missing of_match_table reference 2021-05-10 09:48:17 +02:00
reset-ath79.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
reset-axs10x.c headers: separate linux/mod_devicetable.h from linux/platform_device.h 2018-07-07 17:52:26 +02:00
reset-bcm6345.c reset: bcm6345: Make reset_control_ops const 2021-05-10 09:40:03 +02:00
reset-berlin.c reset: berlin: support module build 2021-06-07 12:45:59 +02:00
reset-brcmstb-rescal.c reset: brcmstb-rescal: fix incorrect polarity of status bit 2021-10-05 10:48:56 +02:00
reset-brcmstb.c reset: brcmstb: Add missing MODULE_DEVICE_TABLE 2021-05-12 08:01:26 +02:00
reset-hsdk.c ARC: HSDK: improve reset driver 2019-01-07 16:38:26 +01:00
reset-imx7.c reset: imx7: Fix the iMX8MP PCIe PHY PERST support 2022-08-30 16:28:48 +02:00
reset-intel-gw.c reset: intel: fix a compile warning about REG_OFFSET redefined 2020-07-20 11:01:19 +02:00
reset-k210.c riscv: Add Canaan Kendryte K210 reset controller 2021-01-14 15:08:53 -08:00
reset-lantiq.c reset: lantiq: use devm_reset_controller_register() 2021-06-07 11:26:31 +02:00
reset-lpc18xx.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
reset-meson-audio-arb.c reset: meson-audio-arb: add sm1 support 2019-10-03 19:56:51 +02:00
reset-meson.c reset: reset-meson: add support for the Meson-S4 SoC Reset Controller 2022-05-03 17:40:51 +02:00
reset-microchip-sparx5.c reset: microchip-sparx5: issue a reset on startup 2022-08-30 16:29:41 +02:00
reset-mpfs.c reset: add polarfire soc reset support 2022-09-14 10:55:17 +03:00
reset-npcm.c reset: npcm: fix iprst2 and iprst4 setting 2022-09-22 17:48:35 +02:00
reset-oxnas.c reset: oxnas: replace file name with short description 2021-05-10 09:40:04 +02:00
reset-pistachio.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422 2019-06-05 17:37:15 +02:00
reset-qcom-aoss.c reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristate 2020-01-08 10:26:14 +01:00
reset-qcom-pdc.c reset: qcom: Add PDC Global reset signals for WPSS 2021-07-21 12:16:17 +02:00
reset-raspberrypi.c reset: raspberrypi: Release firmware handle on unbind 2021-03-22 17:59:51 +01:00
reset-rzg2l-usbphy-ctrl.c reset: renesas: Check return value of reset_control_deassert() 2022-04-04 11:00:27 +02:00
reset-scmi.c reset: reset-scmi: Port driver to the new scmi_reset_proto_ops interface 2021-03-30 16:34:54 +01:00
reset-simple.c reset: simple: Add AST2600 compatible 2022-05-03 17:40:51 +02:00
reset-socfpga.c reset: socfpga: add empty driver allowing consumers to probe 2021-10-05 12:23:16 +02:00
reset-starfive-jh7100.c reset: starfive-jh7100: Fix 32bit compilation 2021-12-20 13:34:00 +01:00
reset-sunplus.c reset: Add Sunplus SP7021 reset driver 2022-07-08 14:23:39 +02:00
reset-sunxi.c reset: Move reset-simple header out of drivers/reset 2020-06-16 14:19:56 +02:00
reset-ti-sci.c treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE 2022-06-10 14:51:36 +02:00
reset-ti-syscon.c treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE 2022-06-10 14:51:36 +02:00
reset-tn48m.c reset: Add Delta TN48M CPLD reset controller 2022-02-25 09:59:35 +01:00
reset-tps380x.c reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage" 2022-07-28 14:08:50 +02:00
reset-uniphier-glue.c reset: uniphier-glue: Use devm_add_action_or_reset() 2022-05-03 17:40:51 +02:00
reset-uniphier.c reset: uniphier: Add NX1 reset support 2021-10-05 11:57:40 +02:00
reset-zynq.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285 2019-06-05 17:36:37 +02:00
reset-zynqmp.c reset: reset-zynqmp: Fixed the argument data type 2021-08-23 12:55:18 +02:00