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The DSDTs of CHT devices using the Dollar Cove TI PMIC, all use LDO1 - LDO14 names for the DSDT power opregion field names. Add comments with these fields to make it easier to see which PMIC registers are being set by ACPI code using these. Note that LDO4 is missing and the mapped registers jump from 0x43 to 0x45 to match. This matches with how the fields are declared in the DSDT where LDO4 is skipped too. Note there is no hole in the field addresses, LDO4 is simply just not defined on either side. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Dollar Cove TI PMIC operation region driver
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* Copyright (C) 2014 Intel Corporation. All rights reserved.
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*
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* Rewritten and cleaned up
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* Copyright (C) 2017 Takashi Iwai <tiwai@suse.de>
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*/
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/platform_device.h>
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#include "intel_pmic.h"
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/* registers stored in 16bit BE (high:low, total 10bit) */
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#define CHTDC_TI_VBAT 0x54
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#define CHTDC_TI_DIETEMP 0x56
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#define CHTDC_TI_BPTHERM 0x58
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#define CHTDC_TI_GPADC 0x5a
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static struct pmic_table chtdc_ti_power_table[] = {
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{ .address = 0x00, .reg = 0x41 }, /* LDO1 */
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{ .address = 0x04, .reg = 0x42 }, /* LDO2 */
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{ .address = 0x08, .reg = 0x43 }, /* LDO3 */
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{ .address = 0x0c, .reg = 0x45 }, /* LDO5 */
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{ .address = 0x10, .reg = 0x46 }, /* LDO6 */
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{ .address = 0x14, .reg = 0x47 }, /* LDO7 */
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{ .address = 0x18, .reg = 0x48 }, /* LDO8 */
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{ .address = 0x1c, .reg = 0x49 }, /* LDO9 */
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{ .address = 0x20, .reg = 0x4a }, /* LD10 */
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{ .address = 0x24, .reg = 0x4b }, /* LD11 */
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{ .address = 0x28, .reg = 0x4c }, /* LD12 */
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{ .address = 0x2c, .reg = 0x4d }, /* LD13 */
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{ .address = 0x30, .reg = 0x4e }, /* LD14 */
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};
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static struct pmic_table chtdc_ti_thermal_table[] = {
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{
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.address = 0x00,
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.reg = CHTDC_TI_GPADC
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},
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{
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.address = 0x0c,
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.reg = CHTDC_TI_GPADC
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},
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/* TMP2 -> SYSTEMP */
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{
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.address = 0x18,
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.reg = CHTDC_TI_GPADC
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},
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/* TMP3 -> BPTHERM */
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{
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.address = 0x24,
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.reg = CHTDC_TI_BPTHERM
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},
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{
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.address = 0x30,
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.reg = CHTDC_TI_GPADC
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},
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/* TMP5 -> DIETEMP */
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{
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.address = 0x3c,
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.reg = CHTDC_TI_DIETEMP
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},
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};
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static int chtdc_ti_pmic_get_power(struct regmap *regmap, int reg, int bit,
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u64 *value)
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{
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int data;
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if (regmap_read(regmap, reg, &data))
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return -EIO;
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*value = data & 1;
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return 0;
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}
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static int chtdc_ti_pmic_update_power(struct regmap *regmap, int reg, int bit,
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bool on)
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{
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return regmap_update_bits(regmap, reg, 1, on);
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}
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static int chtdc_ti_pmic_get_raw_temp(struct regmap *regmap, int reg)
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{
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u8 buf[2];
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if (regmap_bulk_read(regmap, reg, buf, 2))
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return -EIO;
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/* stored in big-endian */
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return ((buf[0] & 0x03) << 8) | buf[1];
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}
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static const struct intel_pmic_opregion_data chtdc_ti_pmic_opregion_data = {
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.get_power = chtdc_ti_pmic_get_power,
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.update_power = chtdc_ti_pmic_update_power,
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.get_raw_temp = chtdc_ti_pmic_get_raw_temp,
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.lpat_raw_to_temp = acpi_lpat_raw_to_temp,
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.power_table = chtdc_ti_power_table,
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.power_table_count = ARRAY_SIZE(chtdc_ti_power_table),
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.thermal_table = chtdc_ti_thermal_table,
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.thermal_table_count = ARRAY_SIZE(chtdc_ti_thermal_table),
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.pmic_i2c_address = 0x5e,
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};
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static int chtdc_ti_pmic_opregion_probe(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
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int err;
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err = intel_pmic_install_opregion_handler(&pdev->dev,
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ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
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&chtdc_ti_pmic_opregion_data);
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if (err < 0)
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return err;
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/* Re-enumerate devices depending on PMIC */
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acpi_dev_clear_dependencies(ACPI_COMPANION(pdev->dev.parent));
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return 0;
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}
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static const struct platform_device_id chtdc_ti_pmic_opregion_id_table[] = {
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{ .name = "chtdc_ti_region" },
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{},
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};
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static struct platform_driver chtdc_ti_pmic_opregion_driver = {
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.probe = chtdc_ti_pmic_opregion_probe,
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.driver = {
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.name = "cht_dollar_cove_ti_pmic",
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},
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.id_table = chtdc_ti_pmic_opregion_id_table,
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};
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builtin_platform_driver(chtdc_ti_pmic_opregion_driver);
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