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Broadcoms DSL, CM (cable modem)and STB I2C core implementation have 8 data in/out registers that can transfer 8 bytes or 32 bytes max. Cable and DSL "Peripheral" i2c cores use single byte per data register and the STB can use 4 byte per data register transfer. Adding support to take care of this difference. Accordingly added the compatible string for SoCs using the "Peripheral" I2C block. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
29 lines
841 B
Plaintext
29 lines
841 B
Plaintext
Broadcom stb bsc iic master controller
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Required properties:
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- compatible: should be "brcm,brcmstb-i2c" or "brcm,brcmper-i2c"
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- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz
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valid values are 375000, 390000, 187500, 200000
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93750, 97500, 46875 and 50000
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- reg: specifies the base physical address and size of the registers
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Optional properties :
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this one is cascaded from
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- interrupts: specifies the interrupt number, the irq line to be used
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- interrupt-names: Interrupt name string
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Example:
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bsca: i2c@f0406200 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&irq0_intc>;
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reg = <0xf0406200 0x58>;
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interrupts = <0x18>;
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interrupt-names = "upg_bsca";
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};
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