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"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
35 lines
1.0 KiB
C
35 lines
1.0 KiB
C
/*
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* linux/arch/arm/mach-mmp/include/mach/addr-map.h
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*
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* Common address map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_ADDR_MAP_H
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#define __ASM_MACH_ADDR_MAP_H
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/* APB - Application Subsystem Peripheral Bus
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*
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* NOTE: the DMA controller registers are actually on the AXI fabric #1
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* slave port to AHB/APB bridge, due to its close relationship to those
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* peripherals on APB, let's count it into the ABP mapping area.
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*/
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#define APB_PHYS_BASE 0xd4000000
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#define APB_VIRT_BASE 0xfe000000
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#define APB_PHYS_SIZE 0x00200000
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#define AXI_PHYS_BASE 0xd4200000
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#define AXI_VIRT_BASE 0xfe200000
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#define AXI_PHYS_SIZE 0x00200000
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/* Static Memory Controller - Chip Select 0 and 1 */
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#define SMC_CS0_PHYS_BASE 0x80000000
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#define SMC_CS0_PHYS_SIZE 0x10000000
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#define SMC_CS1_PHYS_BASE 0x90000000
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#define SMC_CS1_PHYS_SIZE 0x10000000
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#endif /* __ASM_MACH_ADDR_MAP_H */
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