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26a4c991af
Switch from the legacy PCI DMA API to the generic DMA API. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
1872 lines
52 KiB
C
1872 lines
52 KiB
C
/*
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* Copyright 2017 Broadcom. All Rights Reserved.
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* The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@broadcom.com
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*
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*/
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#include <scsi/iscsi_proto.h>
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#include "be_main.h"
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#include "be.h"
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#include "be_mgmt.h"
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/* UE Status Low CSR */
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static const char * const desc_ue_status_low[] = {
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"CEV",
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"CTX",
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"DBUF",
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"ERX",
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"Host",
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"MPU",
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"NDMA",
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"PTC ",
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"RDMA ",
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"RXF ",
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"RXIPS ",
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"RXULP0 ",
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"RXULP1 ",
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"RXULP2 ",
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"TIM ",
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"TPOST ",
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"TPRE ",
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"TXIPS ",
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"TXULP0 ",
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"TXULP1 ",
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"UC ",
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"WDMA ",
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"TXULP2 ",
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"HOST1 ",
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"P0_OB_LINK ",
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"P1_OB_LINK ",
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"HOST_GPIO ",
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"MBOX ",
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"AXGMAC0",
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"AXGMAC1",
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"JTAG",
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"MPU_INTPEND"
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};
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/* UE Status High CSR */
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static const char * const desc_ue_status_hi[] = {
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"LPCMEMHOST",
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"MGMT_MAC",
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"PCS0ONLINE",
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"MPU_IRAM",
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"PCS1ONLINE",
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"PCTL0",
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"PCTL1",
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"PMEM",
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"RR",
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"TXPB",
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"RXPP",
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"XAUI",
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"TXP",
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"ARM",
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"IPC",
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"HOST2",
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"HOST3",
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"HOST4",
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"HOST5",
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"HOST6",
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"HOST7",
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"HOST8",
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"HOST9",
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"NETC",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown"
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};
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struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba,
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unsigned int *ref_tag)
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{
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struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
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struct be_mcc_wrb *wrb = NULL;
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unsigned int tag;
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spin_lock(&phba->ctrl.mcc_lock);
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if (mccq->used == mccq->len) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
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"BC_%d : MCC queue full: WRB used %u tag avail %u\n",
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mccq->used, phba->ctrl.mcc_tag_available);
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goto alloc_failed;
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}
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if (!phba->ctrl.mcc_tag_available)
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goto alloc_failed;
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tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
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if (!tag) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
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"BC_%d : MCC tag 0 allocated: tag avail %u alloc index %u\n",
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phba->ctrl.mcc_tag_available,
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phba->ctrl.mcc_alloc_index);
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goto alloc_failed;
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}
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/* return this tag for further reference */
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*ref_tag = tag;
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phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
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phba->ctrl.mcc_tag_status[tag] = 0;
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phba->ctrl.ptag_state[tag].tag_state = 0;
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phba->ctrl.ptag_state[tag].cbfn = NULL;
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phba->ctrl.mcc_tag_available--;
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if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
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phba->ctrl.mcc_alloc_index = 0;
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else
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phba->ctrl.mcc_alloc_index++;
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wrb = queue_head_node(mccq);
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memset(wrb, 0, sizeof(*wrb));
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wrb->tag0 = tag;
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wrb->tag0 |= (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK;
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queue_head_inc(mccq);
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mccq->used++;
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alloc_failed:
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spin_unlock(&phba->ctrl.mcc_lock);
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return wrb;
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}
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void free_mcc_wrb(struct be_ctrl_info *ctrl, unsigned int tag)
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{
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struct be_queue_info *mccq = &ctrl->mcc_obj.q;
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spin_lock(&ctrl->mcc_lock);
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tag = tag & MCC_Q_CMD_TAG_MASK;
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ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
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if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
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ctrl->mcc_free_index = 0;
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else
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ctrl->mcc_free_index++;
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ctrl->mcc_tag_available++;
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mccq->used--;
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spin_unlock(&ctrl->mcc_lock);
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}
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/*
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* beiscsi_mcc_compl_status - Return the status of MCC completion
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* @phba: Driver private structure
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* @tag: Tag for the MBX Command
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* @wrb: the WRB used for the MBX Command
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* @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
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*
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* return
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* Success: 0
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* Failure: Non-Zero
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*/
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int __beiscsi_mcc_compl_status(struct beiscsi_hba *phba,
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unsigned int tag,
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struct be_mcc_wrb **wrb,
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struct be_dma_mem *mbx_cmd_mem)
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{
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struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
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uint16_t status = 0, addl_status = 0, wrb_num = 0;
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struct be_cmd_resp_hdr *mbx_resp_hdr;
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struct be_cmd_req_hdr *mbx_hdr;
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struct be_mcc_wrb *temp_wrb;
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uint32_t mcc_tag_status;
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int rc = 0;
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mcc_tag_status = phba->ctrl.mcc_tag_status[tag];
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status = (mcc_tag_status & CQE_STATUS_MASK);
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addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >>
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CQE_STATUS_ADDL_SHIFT);
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if (mbx_cmd_mem) {
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mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
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} else {
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wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >>
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CQE_STATUS_WRB_SHIFT;
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temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
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mbx_hdr = embedded_payload(temp_wrb);
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if (wrb)
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*wrb = temp_wrb;
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}
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if (status || addl_status) {
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beiscsi_log(phba, KERN_WARNING,
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BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
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BEISCSI_LOG_CONFIG,
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"BC_%d : MBX Cmd Failed for Subsys : %d Opcode : %d with Status : %d and Extd_Status : %d\n",
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mbx_hdr->subsystem, mbx_hdr->opcode,
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status, addl_status);
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rc = -EIO;
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if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
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mbx_resp_hdr = (struct be_cmd_resp_hdr *)mbx_hdr;
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beiscsi_log(phba, KERN_WARNING,
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BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
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BEISCSI_LOG_CONFIG,
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"BC_%d : Insufficient Buffer Error Resp_Len : %d Actual_Resp_Len : %d\n",
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mbx_resp_hdr->response_length,
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mbx_resp_hdr->actual_resp_len);
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rc = -EAGAIN;
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}
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}
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return rc;
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}
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/*
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* beiscsi_mccq_compl_wait()- Process completion in MCC CQ
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* @phba: Driver private structure
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* @tag: Tag for the MBX Command
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* @wrb: the WRB used for the MBX Command
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* @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
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*
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* Waits for MBX completion with the passed TAG.
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*
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* return
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* Success: 0
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* Failure: Non-Zero
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**/
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int beiscsi_mccq_compl_wait(struct beiscsi_hba *phba,
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unsigned int tag,
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struct be_mcc_wrb **wrb,
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struct be_dma_mem *mbx_cmd_mem)
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{
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int rc = 0;
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if (!tag || tag > MAX_MCC_CMD) {
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__beiscsi_log(phba, KERN_ERR,
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"BC_%d : invalid tag %u\n", tag);
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return -EINVAL;
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}
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if (beiscsi_hba_in_error(phba)) {
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clear_bit(MCC_TAG_STATE_RUNNING,
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&phba->ctrl.ptag_state[tag].tag_state);
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return -EIO;
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}
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/* wait for the mccq completion */
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rc = wait_event_interruptible_timeout(phba->ctrl.mcc_wait[tag],
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phba->ctrl.mcc_tag_status[tag],
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msecs_to_jiffies(
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BEISCSI_HOST_MBX_TIMEOUT));
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/**
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* Return EIO if port is being disabled. Associated DMA memory, if any,
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* is freed by the caller. When port goes offline, MCCQ is cleaned up
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* so does WRB.
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*/
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if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
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clear_bit(MCC_TAG_STATE_RUNNING,
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&phba->ctrl.ptag_state[tag].tag_state);
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return -EIO;
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}
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/**
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* If MBOX cmd timeout expired, tag and resource allocated
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* for cmd is not freed until FW returns completion.
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*/
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if (rc <= 0) {
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struct be_dma_mem *tag_mem;
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/**
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* PCI/DMA memory allocated and posted in non-embedded mode
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* will have mbx_cmd_mem != NULL.
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* Save virtual and bus addresses for the command so that it
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* can be freed later.
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**/
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tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
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if (mbx_cmd_mem) {
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tag_mem->size = mbx_cmd_mem->size;
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tag_mem->va = mbx_cmd_mem->va;
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tag_mem->dma = mbx_cmd_mem->dma;
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} else
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tag_mem->size = 0;
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/* first make tag_mem_state visible to all */
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wmb();
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set_bit(MCC_TAG_STATE_TIMEOUT,
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&phba->ctrl.ptag_state[tag].tag_state);
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
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BEISCSI_LOG_CONFIG,
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"BC_%d : MBX Cmd Completion timed out\n");
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return -EBUSY;
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}
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rc = __beiscsi_mcc_compl_status(phba, tag, wrb, mbx_cmd_mem);
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free_mcc_wrb(&phba->ctrl, tag);
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return rc;
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}
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/*
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* beiscsi_process_mbox_compl()- Check the MBX completion status
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* @ctrl: Function specific MBX data structure
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* @compl: Completion status of MBX Command
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*
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* Check for the MBX completion status when BMBX method used
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*
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* return
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* Success: Zero
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* Failure: Non-Zero
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**/
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static int beiscsi_process_mbox_compl(struct be_ctrl_info *ctrl,
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struct be_mcc_compl *compl)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
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u16 compl_status, extd_status;
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/**
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* To check if valid bit is set, check the entire word as we don't know
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* the endianness of the data (old entry is host endian while a new
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* entry is little endian)
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*/
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if (!compl->flags) {
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beiscsi_log(phba, KERN_ERR,
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BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
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"BC_%d : BMBX busy, no completion\n");
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return -EBUSY;
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}
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compl->flags = le32_to_cpu(compl->flags);
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WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
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/**
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* Just swap the status to host endian;
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* mcc tag is opaquely copied from mcc_wrb.
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*/
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be_dws_le_to_cpu(compl, 4);
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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/* Need to reset the entire word that houses the valid bit */
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compl->flags = 0;
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if (compl_status == MCC_STATUS_SUCCESS)
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return 0;
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
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"BC_%d : error in cmd completion: Subsystem : %d Opcode : %d status(compl/extd)=%d/%d\n",
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hdr->subsystem, hdr->opcode, compl_status, extd_status);
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return compl_status;
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}
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static void beiscsi_process_async_link(struct beiscsi_hba *phba,
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struct be_mcc_compl *compl)
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{
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struct be_async_event_link_state *evt;
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evt = (struct be_async_event_link_state *)compl;
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phba->port_speed = evt->port_speed;
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/**
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* Check logical link status in ASYNC event.
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* This has been newly introduced in SKH-R Firmware 10.0.338.45.
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**/
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if (evt->port_link_status & BE_ASYNC_LINK_UP_MASK) {
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set_bit(BEISCSI_HBA_LINK_UP, &phba->state);
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if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
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beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
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__beiscsi_log(phba, KERN_ERR,
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"BC_%d : Link Up on Port %d tag 0x%x\n",
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evt->physical_port, evt->event_tag);
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} else {
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clear_bit(BEISCSI_HBA_LINK_UP, &phba->state);
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__beiscsi_log(phba, KERN_ERR,
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"BC_%d : Link Down on Port %d tag 0x%x\n",
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evt->physical_port, evt->event_tag);
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iscsi_host_for_each_session(phba->shost,
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beiscsi_session_fail);
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}
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}
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static char *beiscsi_port_misconf_event_msg[] = {
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"Physical Link is functional.",
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"Optics faulted/incorrectly installed/not installed - Reseat optics, if issue not resolved, replace.",
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"Optics of two types installed - Remove one optic or install matching pair of optics.",
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"Incompatible optics - Replace with compatible optics for card to function.",
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"Unqualified optics - Replace with Avago optics for Warranty and Technical Support.",
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"Uncertified optics - Replace with Avago Certified optics to enable link operation."
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};
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static void beiscsi_process_async_sli(struct beiscsi_hba *phba,
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struct be_mcc_compl *compl)
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{
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struct be_async_event_sli *async_sli;
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u8 evt_type, state, old_state, le;
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char *sev = KERN_WARNING;
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char *msg = NULL;
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evt_type = compl->flags >> ASYNC_TRAILER_EVENT_TYPE_SHIFT;
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evt_type &= ASYNC_TRAILER_EVENT_TYPE_MASK;
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/* processing only MISCONFIGURED physical port event */
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if (evt_type != ASYNC_SLI_EVENT_TYPE_MISCONFIGURED)
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return;
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async_sli = (struct be_async_event_sli *)compl;
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state = async_sli->event_data1 >>
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(phba->fw_config.phys_port * 8) & 0xff;
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le = async_sli->event_data2 >>
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(phba->fw_config.phys_port * 8) & 0xff;
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old_state = phba->optic_state;
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phba->optic_state = state;
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if (state >= ARRAY_SIZE(beiscsi_port_misconf_event_msg)) {
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/* fw is reporting a state we don't know, log and return */
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__beiscsi_log(phba, KERN_ERR,
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"BC_%d : Port %c: Unrecognized optic state 0x%x\n",
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phba->port_name, async_sli->event_data1);
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return;
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}
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if (ASYNC_SLI_LINK_EFFECT_VALID(le)) {
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/* log link effect for unqualified-4, uncertified-5 optics */
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if (state > 3)
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msg = (ASYNC_SLI_LINK_EFFECT_STATE(le)) ?
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" Link is non-operational." :
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" Link is operational.";
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/* 1 - info */
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if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 1)
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sev = KERN_INFO;
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/* 2 - error */
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if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 2)
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sev = KERN_ERR;
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}
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if (old_state != phba->optic_state)
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__beiscsi_log(phba, sev, "BC_%d : Port %c: %s%s\n",
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phba->port_name,
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beiscsi_port_misconf_event_msg[state],
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!msg ? "" : msg);
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}
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|
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void beiscsi_process_async_event(struct beiscsi_hba *phba,
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struct be_mcc_compl *compl)
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{
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char *sev = KERN_INFO;
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u8 evt_code;
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|
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/* interpret flags as an async trailer */
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evt_code = compl->flags >> ASYNC_TRAILER_EVENT_CODE_SHIFT;
|
|
evt_code &= ASYNC_TRAILER_EVENT_CODE_MASK;
|
|
switch (evt_code) {
|
|
case ASYNC_EVENT_CODE_LINK_STATE:
|
|
beiscsi_process_async_link(phba, compl);
|
|
break;
|
|
case ASYNC_EVENT_CODE_ISCSI:
|
|
if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
|
|
beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
|
|
sev = KERN_ERR;
|
|
break;
|
|
case ASYNC_EVENT_CODE_SLI:
|
|
beiscsi_process_async_sli(phba, compl);
|
|
break;
|
|
default:
|
|
/* event not registered */
|
|
sev = KERN_ERR;
|
|
}
|
|
|
|
beiscsi_log(phba, sev, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
|
|
"BC_%d : ASYNC Event %x: status 0x%08x flags 0x%08x\n",
|
|
evt_code, compl->status, compl->flags);
|
|
}
|
|
|
|
int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl,
|
|
struct be_mcc_compl *compl)
|
|
{
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
u16 compl_status, extd_status;
|
|
struct be_dma_mem *tag_mem;
|
|
unsigned int tag, wrb_idx;
|
|
|
|
be_dws_le_to_cpu(compl, 4);
|
|
tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);
|
|
wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;
|
|
|
|
if (!test_bit(MCC_TAG_STATE_RUNNING,
|
|
&ctrl->ptag_state[tag].tag_state)) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX |
|
|
BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
|
|
"BC_%d : MBX cmd completed but not posted\n");
|
|
return 0;
|
|
}
|
|
|
|
/* end MCC with this tag */
|
|
clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
|
|
|
|
if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) {
|
|
beiscsi_log(phba, KERN_WARNING,
|
|
BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
|
|
BEISCSI_LOG_CONFIG,
|
|
"BC_%d : MBX Completion for timeout Command from FW\n");
|
|
/**
|
|
* Check for the size before freeing resource.
|
|
* Only for non-embedded cmd, PCI resource is allocated.
|
|
**/
|
|
tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
|
|
if (tag_mem->size) {
|
|
dma_free_coherent(&ctrl->pdev->dev, tag_mem->size,
|
|
tag_mem->va, tag_mem->dma);
|
|
tag_mem->size = 0;
|
|
}
|
|
free_mcc_wrb(ctrl, tag);
|
|
return 0;
|
|
}
|
|
|
|
compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
|
|
CQE_STATUS_COMPL_MASK;
|
|
extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
|
|
CQE_STATUS_EXTD_MASK;
|
|
/* The ctrl.mcc_tag_status[tag] is filled with
|
|
* [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
|
|
* [7:0] = compl_status
|
|
*/
|
|
ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;
|
|
ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);
|
|
ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &
|
|
CQE_STATUS_ADDL_MASK;
|
|
ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);
|
|
|
|
if (test_bit(MCC_TAG_STATE_ASYNC, &ctrl->ptag_state[tag].tag_state)) {
|
|
if (ctrl->ptag_state[tag].cbfn)
|
|
ctrl->ptag_state[tag].cbfn(phba, tag);
|
|
else
|
|
__beiscsi_log(phba, KERN_ERR,
|
|
"BC_%d : MBX ASYNC command with no callback\n");
|
|
free_mcc_wrb(ctrl, tag);
|
|
return 0;
|
|
}
|
|
|
|
if (test_bit(MCC_TAG_STATE_IGNORE, &ctrl->ptag_state[tag].tag_state)) {
|
|
/* just check completion status and free wrb */
|
|
__beiscsi_mcc_compl_status(phba, tag, NULL, NULL);
|
|
free_mcc_wrb(ctrl, tag);
|
|
return 0;
|
|
}
|
|
|
|
wake_up_interruptible(&ctrl->mcc_wait[tag]);
|
|
return 0;
|
|
}
|
|
|
|
void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag)
|
|
{
|
|
struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
|
|
u32 val = 0;
|
|
|
|
set_bit(MCC_TAG_STATE_RUNNING, &phba->ctrl.ptag_state[tag].tag_state);
|
|
val |= mccq->id & DB_MCCQ_RING_ID_MASK;
|
|
val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
|
|
/* make request available for DMA */
|
|
wmb();
|
|
iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
|
|
}
|
|
|
|
/*
|
|
* be_mbox_db_ready_poll()- Check ready status
|
|
* @ctrl: Function specific MBX data structure
|
|
*
|
|
* Check for the ready status of FW to send BMBX
|
|
* commands to adapter.
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero
|
|
**/
|
|
static int be_mbox_db_ready_poll(struct be_ctrl_info *ctrl)
|
|
{
|
|
/* wait 30s for generic non-flash MBOX operation */
|
|
#define BEISCSI_MBX_RDY_BIT_TIMEOUT 30000
|
|
void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
unsigned long timeout;
|
|
u32 ready;
|
|
|
|
/*
|
|
* This BMBX busy wait path is used during init only.
|
|
* For the commands executed during init, 5s should suffice.
|
|
*/
|
|
timeout = jiffies + msecs_to_jiffies(BEISCSI_MBX_RDY_BIT_TIMEOUT);
|
|
do {
|
|
if (beiscsi_hba_in_error(phba))
|
|
return -EIO;
|
|
|
|
ready = ioread32(db);
|
|
if (ready == 0xffffffff)
|
|
return -EIO;
|
|
|
|
ready &= MPU_MAILBOX_DB_RDY_MASK;
|
|
if (ready)
|
|
return 0;
|
|
|
|
if (time_after(jiffies, timeout))
|
|
break;
|
|
/* 1ms sleep is enough in most cases */
|
|
schedule_timeout_uninterruptible(msecs_to_jiffies(1));
|
|
} while (!ready);
|
|
|
|
beiscsi_log(phba, KERN_ERR,
|
|
BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
|
|
"BC_%d : FW Timed Out\n");
|
|
set_bit(BEISCSI_HBA_FW_TIMEOUT, &phba->state);
|
|
return -EBUSY;
|
|
}
|
|
|
|
/*
|
|
* be_mbox_notify: Notify adapter of new BMBX command
|
|
* @ctrl: Function specific MBX data structure
|
|
*
|
|
* Ring doorbell to inform adapter of a BMBX command
|
|
* to process
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero
|
|
**/
|
|
static int be_mbox_notify(struct be_ctrl_info *ctrl)
|
|
{
|
|
int status;
|
|
u32 val = 0;
|
|
void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
|
|
struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
|
|
struct be_mcc_mailbox *mbox = mbox_mem->va;
|
|
|
|
status = be_mbox_db_ready_poll(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
val &= ~MPU_MAILBOX_DB_RDY_MASK;
|
|
val |= MPU_MAILBOX_DB_HI_MASK;
|
|
val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
|
|
iowrite32(val, db);
|
|
|
|
status = be_mbox_db_ready_poll(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
val = 0;
|
|
val &= ~MPU_MAILBOX_DB_RDY_MASK;
|
|
val &= ~MPU_MAILBOX_DB_HI_MASK;
|
|
val |= (u32) (mbox_mem->dma >> 4) << 2;
|
|
iowrite32(val, db);
|
|
|
|
status = be_mbox_db_ready_poll(ctrl);
|
|
if (status)
|
|
return status;
|
|
|
|
/* RDY is set; small delay before CQE read. */
|
|
udelay(1);
|
|
|
|
status = beiscsi_process_mbox_compl(ctrl, &mbox->compl);
|
|
return status;
|
|
}
|
|
|
|
void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, u32 payload_len,
|
|
bool embedded, u8 sge_cnt)
|
|
{
|
|
if (embedded)
|
|
wrb->emb_sgecnt_special |= MCC_WRB_EMBEDDED_MASK;
|
|
else
|
|
wrb->emb_sgecnt_special |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
|
|
MCC_WRB_SGE_CNT_SHIFT;
|
|
wrb->payload_length = payload_len;
|
|
be_dws_cpu_to_le(wrb, 8);
|
|
}
|
|
|
|
void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
|
|
u8 subsystem, u8 opcode, u32 cmd_len)
|
|
{
|
|
req_hdr->opcode = opcode;
|
|
req_hdr->subsystem = subsystem;
|
|
req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
|
|
req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
|
|
}
|
|
|
|
static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
|
|
struct be_dma_mem *mem)
|
|
{
|
|
int i, buf_pages;
|
|
u64 dma = (u64) mem->dma;
|
|
|
|
buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
|
|
for (i = 0; i < buf_pages; i++) {
|
|
pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
|
|
pages[i].hi = cpu_to_le32(upper_32_bits(dma));
|
|
dma += PAGE_SIZE_4K;
|
|
}
|
|
}
|
|
|
|
static u32 eq_delay_to_mult(u32 usec_delay)
|
|
{
|
|
#define MAX_INTR_RATE 651042
|
|
const u32 round = 10;
|
|
u32 multiplier;
|
|
|
|
if (usec_delay == 0)
|
|
multiplier = 0;
|
|
else {
|
|
u32 interrupt_rate = 1000000 / usec_delay;
|
|
if (interrupt_rate == 0)
|
|
multiplier = 1023;
|
|
else {
|
|
multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
|
|
multiplier /= interrupt_rate;
|
|
multiplier = (multiplier + round / 2) / round;
|
|
multiplier = min(multiplier, (u32) 1023);
|
|
}
|
|
}
|
|
return multiplier;
|
|
}
|
|
|
|
struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
|
|
{
|
|
return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
|
|
}
|
|
|
|
int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *eq, int eq_delay)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_eq_create *req = embedded_payload(wrb);
|
|
struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &eq->dma_mem;
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_EQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
|
|
|
AMAP_SET_BITS(struct amap_eq_context, func, req->context,
|
|
PCI_FUNC(ctrl->pdev->devfn));
|
|
AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
|
|
AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
|
|
AMAP_SET_BITS(struct amap_eq_context, count, req->context,
|
|
__ilog2_u32(eq->len / 256));
|
|
AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
|
|
eq_delay_to_mult(eq_delay));
|
|
be_dws_cpu_to_le(req->context, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
eq->id = le16_to_cpu(resp->eq_id);
|
|
eq->created = true;
|
|
}
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *cq, struct be_queue_info *eq,
|
|
bool sol_evts, bool no_delay, int coalesce_wm)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_cq_create *req = embedded_payload(wrb);
|
|
struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
struct be_dma_mem *q_mem = &cq->dma_mem;
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_CQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
|
if (is_chip_be2_be3r(phba)) {
|
|
AMAP_SET_BITS(struct amap_cq_context, coalescwm,
|
|
ctxt, coalesce_wm);
|
|
AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
|
|
AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
|
|
__ilog2_u32(cq->len / 256));
|
|
AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
|
|
AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
|
|
AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
|
|
PCI_FUNC(ctrl->pdev->devfn));
|
|
} else {
|
|
req->hdr.version = MBX_CMD_VER2;
|
|
req->page_size = 1;
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
|
|
ctxt, coalesce_wm);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
|
|
ctxt, no_delay);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
|
|
__ilog2_u32(cq->len / 256));
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
|
|
AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
|
|
}
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
cq->id = le16_to_cpu(resp->cq_id);
|
|
cq->created = true;
|
|
} else
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : In be_cmd_cq_create, status=ox%08x\n",
|
|
status);
|
|
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
static u32 be_encoded_q_len(int q_len)
|
|
{
|
|
u32 len_encoded = fls(q_len); /* log2(len) + 1 */
|
|
if (len_encoded == 16)
|
|
len_encoded = 0;
|
|
return len_encoded;
|
|
}
|
|
|
|
int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
|
|
struct be_queue_info *mccq,
|
|
struct be_queue_info *cq)
|
|
{
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_req_mcc_create_ext *req;
|
|
struct be_dma_mem *q_mem = &mccq->dma_mem;
|
|
struct be_ctrl_info *ctrl;
|
|
void *ctxt;
|
|
int status;
|
|
|
|
mutex_lock(&phba->ctrl.mbox_lock);
|
|
ctrl = &phba->ctrl;
|
|
wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
req = embedded_payload(wrb);
|
|
ctxt = &req->context;
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
req->async_evt_bitmap = 1 << ASYNC_EVENT_CODE_LINK_STATE;
|
|
req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_ISCSI;
|
|
req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_SLI;
|
|
|
|
AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
|
|
PCI_FUNC(phba->pcidev->devfn));
|
|
AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
|
|
be_encoded_q_len(mccq->len));
|
|
AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
|
|
mccq->id = le16_to_cpu(resp->id);
|
|
mccq->created = true;
|
|
}
|
|
mutex_unlock(&phba->ctrl.mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
|
|
int queue_type)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
u8 subsys = 0, opcode = 0;
|
|
int status;
|
|
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BC_%d : In beiscsi_cmd_q_destroy "
|
|
"queue_type : %d\n", queue_type);
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
switch (queue_type) {
|
|
case QTYPE_EQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_EQ_DESTROY;
|
|
break;
|
|
case QTYPE_CQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_CQ_DESTROY;
|
|
break;
|
|
case QTYPE_MCCQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_MCC_DESTROY;
|
|
break;
|
|
case QTYPE_WRBQ:
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
|
opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
|
|
break;
|
|
case QTYPE_DPDUQ:
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
|
opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
|
|
break;
|
|
case QTYPE_SGL:
|
|
subsys = CMD_SUBSYSTEM_ISCSI;
|
|
opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
|
|
break;
|
|
default:
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
BUG();
|
|
}
|
|
be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
|
|
if (queue_type != QTYPE_SGL)
|
|
req->id = cpu_to_le16(q->id);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
|
|
* @ctrl: ptr to ctrl_info
|
|
* @cq: Completion Queue
|
|
* @dq: Default Queue
|
|
* @lenght: ring size
|
|
* @entry_size: size of each entry in DEFQ
|
|
* @is_header: Header or Data DEFQ
|
|
* @ulp_num: Bind to which ULP
|
|
*
|
|
* Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
|
|
* on this queue by the FW
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero Value
|
|
*
|
|
**/
|
|
int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *cq,
|
|
struct be_queue_info *dq, int length,
|
|
int entry_size, uint8_t is_header,
|
|
uint8_t ulp_num)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_defq_create_req *req = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &dq->dma_mem;
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
if (phba->fw_config.dual_ulp_aware) {
|
|
req->ulp_num = ulp_num;
|
|
req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
|
|
req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
|
|
}
|
|
|
|
if (is_chip_be2_be3r(phba)) {
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
rx_pdid, ctxt, 0);
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
rx_pdid_valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
ring_size, ctxt,
|
|
be_encoded_q_len(length /
|
|
sizeof(struct phys_addr)));
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
default_buffer_size, ctxt, entry_size);
|
|
AMAP_SET_BITS(struct amap_be_default_pdu_context,
|
|
cq_id_recv, ctxt, cq->id);
|
|
} else {
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
rx_pdid, ctxt, 0);
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
rx_pdid_valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
ring_size, ctxt,
|
|
be_encoded_q_len(length /
|
|
sizeof(struct phys_addr)));
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
default_buffer_size, ctxt, entry_size);
|
|
AMAP_SET_BITS(struct amap_default_pdu_context_ext,
|
|
cq_id_recv, ctxt, cq->id);
|
|
}
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
struct be_ring *defq_ring;
|
|
struct be_defq_create_resp *resp = embedded_payload(wrb);
|
|
|
|
dq->id = le16_to_cpu(resp->id);
|
|
dq->created = true;
|
|
if (is_header)
|
|
defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
|
|
else
|
|
defq_ring = &phba->phwi_ctrlr->
|
|
default_pdu_data[ulp_num];
|
|
|
|
defq_ring->id = dq->id;
|
|
|
|
if (!phba->fw_config.dual_ulp_aware) {
|
|
defq_ring->ulp_num = BEISCSI_ULP0;
|
|
defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
|
|
} else {
|
|
defq_ring->ulp_num = resp->ulp_num;
|
|
defq_ring->doorbell_offset = resp->doorbell_offset;
|
|
}
|
|
}
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* be_cmd_wrbq_create()- Create WRBQ
|
|
* @ctrl: ptr to ctrl_info
|
|
* @q_mem: memory details for the queue
|
|
* @wrbq: queue info
|
|
* @pwrb_context: ptr to wrb_context
|
|
* @ulp_num: ULP on which the WRBQ is to be created
|
|
*
|
|
* Create WRBQ on the passed ULP_NUM.
|
|
*
|
|
**/
|
|
int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
|
|
struct be_dma_mem *q_mem,
|
|
struct be_queue_info *wrbq,
|
|
struct hwi_wrb_context *pwrb_context,
|
|
uint8_t ulp_num)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_wrbq_create_req *req = embedded_payload(wrb);
|
|
struct be_wrbq_create_resp *resp = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
|
|
if (phba->fw_config.dual_ulp_aware) {
|
|
req->ulp_num = ulp_num;
|
|
req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
|
|
req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
|
|
}
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
wrbq->id = le16_to_cpu(resp->cid);
|
|
wrbq->created = true;
|
|
|
|
pwrb_context->cid = wrbq->id;
|
|
if (!phba->fw_config.dual_ulp_aware) {
|
|
pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
|
|
pwrb_context->ulp_num = BEISCSI_ULP0;
|
|
} else {
|
|
pwrb_context->ulp_num = resp->ulp_num;
|
|
pwrb_context->doorbell_offset = resp->doorbell_offset;
|
|
}
|
|
}
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
|
|
struct be_dma_mem *q_mem)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_post_template_pages_req *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
|
|
sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_remove_template_pages_req *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
|
|
sizeof(*req));
|
|
|
|
req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
|
|
struct be_dma_mem *q_mem,
|
|
u32 page_offset, u32 num_pages)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_post_sgl_pages_req *req = embedded_payload(wrb);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
int status;
|
|
unsigned int curr_pages;
|
|
u32 internal_page_offset = 0;
|
|
u32 temp_num_pages = num_pages;
|
|
|
|
if (num_pages == 0xff)
|
|
num_pages = 1;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
do {
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
|
|
sizeof(*req));
|
|
curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
|
|
pages);
|
|
req->num_pages = min(num_pages, curr_pages);
|
|
req->page_offset = page_offset;
|
|
be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
|
|
q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
|
|
internal_page_offset += req->num_pages;
|
|
page_offset += req->num_pages;
|
|
num_pages -= req->num_pages;
|
|
|
|
if (temp_num_pages == 0xff)
|
|
req->num_pages = temp_num_pages;
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (status) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : FW CMD to map iscsi frags failed.\n");
|
|
|
|
goto error;
|
|
}
|
|
} while (num_pages > 0);
|
|
error:
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
if (status != 0)
|
|
beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* be_cmd_set_vlan()- Configure VLAN paramters on the adapter
|
|
* @phba: device priv structure instance
|
|
* @vlan_tag: TAG to be set
|
|
*
|
|
* Set the VLAN_TAG for the adapter or Disable VLAN on adapter
|
|
*
|
|
* returns
|
|
* TAG for the MBX Cmd
|
|
* **/
|
|
int be_cmd_set_vlan(struct beiscsi_hba *phba,
|
|
uint16_t vlan_tag)
|
|
{
|
|
unsigned int tag;
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_set_vlan_req *req;
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
|
|
if (mutex_lock_interruptible(&ctrl->mbox_lock))
|
|
return 0;
|
|
wrb = alloc_mcc_wrb(phba, &tag);
|
|
if (!wrb) {
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return 0;
|
|
}
|
|
|
|
req = embedded_payload(wrb);
|
|
be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
|
|
sizeof(*req));
|
|
|
|
req->interface_hndl = phba->interface_handle;
|
|
req->vlan_priority = vlan_tag;
|
|
|
|
be_mcc_notify(phba, tag);
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
|
|
return tag;
|
|
}
|
|
|
|
int beiscsi_check_supported_fw(struct be_ctrl_info *ctrl,
|
|
struct beiscsi_hba *phba)
|
|
{
|
|
struct be_dma_mem nonemb_cmd;
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_mgmt_controller_attributes *req;
|
|
struct be_sge *sge = nonembedded_sgl(wrb);
|
|
int status = 0;
|
|
|
|
nonemb_cmd.va = dma_alloc_coherent(&ctrl->pdev->dev,
|
|
sizeof(struct be_mgmt_controller_attributes),
|
|
&nonemb_cmd.dma, GFP_KERNEL);
|
|
if (nonemb_cmd.va == NULL) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : dma_alloc_coherent failed in %s\n",
|
|
__func__);
|
|
return -ENOMEM;
|
|
}
|
|
nonemb_cmd.size = sizeof(struct be_mgmt_controller_attributes);
|
|
req = nonemb_cmd.va;
|
|
memset(req, 0, sizeof(*req));
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_GET_CNTL_ATTRIBUTES, sizeof(*req));
|
|
sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma));
|
|
sge->pa_lo = cpu_to_le32(nonemb_cmd.dma & 0xFFFFFFFF);
|
|
sge->len = cpu_to_le32(nonemb_cmd.size);
|
|
status = be_mbox_notify(ctrl);
|
|
if (!status) {
|
|
struct be_mgmt_controller_attributes_resp *resp = nonemb_cmd.va;
|
|
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : Firmware Version of CMD : %s\n"
|
|
"Firmware Version is : %s\n"
|
|
"Developer Build, not performing version check...\n",
|
|
resp->params.hba_attribs
|
|
.flashrom_version_string,
|
|
resp->params.hba_attribs.
|
|
firmware_version_string);
|
|
|
|
phba->fw_config.iscsi_features =
|
|
resp->params.hba_attribs.iscsi_features;
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BM_%d : phba->fw_config.iscsi_features = %d\n",
|
|
phba->fw_config.iscsi_features);
|
|
memcpy(phba->fw_ver_str, resp->params.hba_attribs.
|
|
firmware_version_string, BEISCSI_VER_STRLEN);
|
|
} else
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : Failed in beiscsi_check_supported_fw\n");
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
if (nonemb_cmd.va)
|
|
dma_free_coherent(&ctrl->pdev->dev, nonemb_cmd.size,
|
|
nonemb_cmd.va, nonemb_cmd.dma);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* beiscsi_get_fw_config()- Get the FW config for the function
|
|
* @ctrl: ptr to Ctrl Info
|
|
* @phba: ptr to the dev priv structure
|
|
*
|
|
* Get the FW config and resources available for the function.
|
|
* The resources are created based on the count received here.
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero Value
|
|
**/
|
|
int beiscsi_get_fw_config(struct be_ctrl_info *ctrl,
|
|
struct beiscsi_hba *phba)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_fw_cfg *pfw_cfg = embedded_payload(wrb);
|
|
uint32_t cid_count, icd_count;
|
|
int status = -EINVAL;
|
|
uint8_t ulp_num = 0;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*pfw_cfg), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&pfw_cfg->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
|
|
EMBED_MBX_MAX_PAYLOAD_SIZE);
|
|
|
|
if (be_mbox_notify(ctrl)) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : Failed in beiscsi_get_fw_config\n");
|
|
goto fail_init;
|
|
}
|
|
|
|
/* FW response formats depend on port id */
|
|
phba->fw_config.phys_port = pfw_cfg->phys_port;
|
|
if (phba->fw_config.phys_port >= BEISCSI_PHYS_PORT_MAX) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : invalid physical port id %d\n",
|
|
phba->fw_config.phys_port);
|
|
goto fail_init;
|
|
}
|
|
|
|
/* populate and check FW config against min and max values */
|
|
if (!is_chip_be2_be3r(phba)) {
|
|
phba->fw_config.eqid_count = pfw_cfg->eqid_count;
|
|
phba->fw_config.cqid_count = pfw_cfg->cqid_count;
|
|
if (phba->fw_config.eqid_count == 0 ||
|
|
phba->fw_config.eqid_count > 2048) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : invalid EQ count %d\n",
|
|
phba->fw_config.eqid_count);
|
|
goto fail_init;
|
|
}
|
|
if (phba->fw_config.cqid_count == 0 ||
|
|
phba->fw_config.cqid_count > 4096) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : invalid CQ count %d\n",
|
|
phba->fw_config.cqid_count);
|
|
goto fail_init;
|
|
}
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : EQ_Count : %d CQ_Count : %d\n",
|
|
phba->fw_config.eqid_count,
|
|
phba->fw_config.cqid_count);
|
|
}
|
|
|
|
/**
|
|
* Check on which all ULP iSCSI Protocol is loaded.
|
|
* Set the Bit for those ULP. This set flag is used
|
|
* at all places in the code to check on which ULP
|
|
* iSCSi Protocol is loaded
|
|
**/
|
|
for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
|
|
if (pfw_cfg->ulp[ulp_num].ulp_mode &
|
|
BEISCSI_ULP_ISCSI_INI_MODE) {
|
|
set_bit(ulp_num, &phba->fw_config.ulp_supported);
|
|
|
|
/* Get the CID, ICD and Chain count for each ULP */
|
|
phba->fw_config.iscsi_cid_start[ulp_num] =
|
|
pfw_cfg->ulp[ulp_num].sq_base;
|
|
phba->fw_config.iscsi_cid_count[ulp_num] =
|
|
pfw_cfg->ulp[ulp_num].sq_count;
|
|
|
|
phba->fw_config.iscsi_icd_start[ulp_num] =
|
|
pfw_cfg->ulp[ulp_num].icd_base;
|
|
phba->fw_config.iscsi_icd_count[ulp_num] =
|
|
pfw_cfg->ulp[ulp_num].icd_count;
|
|
|
|
phba->fw_config.iscsi_chain_start[ulp_num] =
|
|
pfw_cfg->chain_icd[ulp_num].chain_base;
|
|
phba->fw_config.iscsi_chain_count[ulp_num] =
|
|
pfw_cfg->chain_icd[ulp_num].chain_count;
|
|
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : Function loaded on ULP : %d\n"
|
|
"\tiscsi_cid_count : %d\n"
|
|
"\tiscsi_cid_start : %d\n"
|
|
"\t iscsi_icd_count : %d\n"
|
|
"\t iscsi_icd_start : %d\n",
|
|
ulp_num,
|
|
phba->fw_config.
|
|
iscsi_cid_count[ulp_num],
|
|
phba->fw_config.
|
|
iscsi_cid_start[ulp_num],
|
|
phba->fw_config.
|
|
iscsi_icd_count[ulp_num],
|
|
phba->fw_config.
|
|
iscsi_icd_start[ulp_num]);
|
|
}
|
|
}
|
|
|
|
if (phba->fw_config.ulp_supported == 0) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d : iSCSI initiator mode not set: ULP0 %x ULP1 %x\n",
|
|
pfw_cfg->ulp[BEISCSI_ULP0].ulp_mode,
|
|
pfw_cfg->ulp[BEISCSI_ULP1].ulp_mode);
|
|
goto fail_init;
|
|
}
|
|
|
|
/**
|
|
* ICD is shared among ULPs. Use icd_count of any one loaded ULP
|
|
**/
|
|
for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
|
|
if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
|
|
break;
|
|
icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
|
|
if (icd_count == 0 || icd_count > 65536) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d: invalid ICD count %d\n", icd_count);
|
|
goto fail_init;
|
|
}
|
|
|
|
cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
|
|
BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
|
|
if (cid_count == 0 || cid_count > 4096) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BG_%d: invalid CID count %d\n", cid_count);
|
|
goto fail_init;
|
|
}
|
|
|
|
/**
|
|
* Check FW is dual ULP aware i.e. can handle either
|
|
* of the protocols.
|
|
*/
|
|
phba->fw_config.dual_ulp_aware = (pfw_cfg->function_mode &
|
|
BEISCSI_FUNC_DUA_MODE);
|
|
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : DUA Mode : 0x%x\n",
|
|
phba->fw_config.dual_ulp_aware);
|
|
|
|
/* all set, continue using this FW config */
|
|
status = 0;
|
|
fail_init:
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* beiscsi_get_port_name()- Get port name for the function
|
|
* @ctrl: ptr to Ctrl Info
|
|
* @phba: ptr to the dev priv structure
|
|
*
|
|
* Get the alphanumeric character for port
|
|
*
|
|
**/
|
|
int beiscsi_get_port_name(struct be_ctrl_info *ctrl, struct beiscsi_hba *phba)
|
|
{
|
|
int ret = 0;
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_get_port_name *ioctl;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
ioctl = embedded_payload(wrb);
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
|
|
be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_GET_PORT_NAME,
|
|
EMBED_MBX_MAX_PAYLOAD_SIZE);
|
|
ret = be_mbox_notify(ctrl);
|
|
phba->port_name = 0;
|
|
if (!ret) {
|
|
phba->port_name = ioctl->p.resp.port_names >>
|
|
(phba->fw_config.phys_port * 8) & 0xff;
|
|
} else {
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : GET_PORT_NAME ret 0x%x status 0x%x\n",
|
|
ret, ioctl->h.resp_hdr.status);
|
|
}
|
|
|
|
if (phba->port_name == 0)
|
|
phba->port_name = '?';
|
|
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return ret;
|
|
}
|
|
|
|
int beiscsi_set_host_data(struct beiscsi_hba *phba)
|
|
{
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
struct be_cmd_set_host_data *ioctl;
|
|
struct be_mcc_wrb *wrb;
|
|
int ret = 0;
|
|
|
|
if (is_chip_be2_be3r(phba))
|
|
return ret;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
ioctl = embedded_payload(wrb);
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
|
|
be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_SET_HOST_DATA,
|
|
EMBED_MBX_MAX_PAYLOAD_SIZE);
|
|
ioctl->param.req.param_id = BE_CMD_SET_HOST_PARAM_ID;
|
|
ioctl->param.req.param_len =
|
|
snprintf((char *)ioctl->param.req.param_data,
|
|
sizeof(ioctl->param.req.param_data),
|
|
"Linux iSCSI v%s", BUILD_STR);
|
|
ioctl->param.req.param_len = ALIGN(ioctl->param.req.param_len + 1, 4);
|
|
if (ioctl->param.req.param_len > BE_CMD_MAX_DRV_VERSION)
|
|
ioctl->param.req.param_len = BE_CMD_MAX_DRV_VERSION;
|
|
ret = be_mbox_notify(ctrl);
|
|
if (!ret) {
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : HBA set host driver version\n");
|
|
} else {
|
|
/**
|
|
* Check "MCC_STATUS_INVALID_LENGTH" for SKH.
|
|
* Older FW versions return this error.
|
|
*/
|
|
if (ret == MCC_STATUS_ILLEGAL_REQUEST ||
|
|
ret == MCC_STATUS_INVALID_LENGTH)
|
|
__beiscsi_log(phba, KERN_INFO,
|
|
"BG_%d : HBA failed to set host driver version\n");
|
|
}
|
|
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return ret;
|
|
}
|
|
|
|
int beiscsi_set_uer_feature(struct beiscsi_hba *phba)
|
|
{
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
struct be_cmd_set_features *ioctl;
|
|
struct be_mcc_wrb *wrb;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
ioctl = embedded_payload(wrb);
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
|
|
be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_SET_FEATURES,
|
|
EMBED_MBX_MAX_PAYLOAD_SIZE);
|
|
ioctl->feature = BE_CMD_SET_FEATURE_UER;
|
|
ioctl->param_len = sizeof(ioctl->param.req);
|
|
ioctl->param.req.uer = BE_CMD_UER_SUPP_BIT;
|
|
ret = be_mbox_notify(ctrl);
|
|
if (!ret) {
|
|
phba->ue2rp = ioctl->param.resp.ue2rp;
|
|
set_bit(BEISCSI_HBA_UER_SUPP, &phba->state);
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BG_%d : HBA error recovery supported\n");
|
|
} else {
|
|
/**
|
|
* Check "MCC_STATUS_INVALID_LENGTH" for SKH.
|
|
* Older FW versions return this error.
|
|
*/
|
|
if (ret == MCC_STATUS_ILLEGAL_REQUEST ||
|
|
ret == MCC_STATUS_INVALID_LENGTH)
|
|
__beiscsi_log(phba, KERN_INFO,
|
|
"BG_%d : HBA error recovery not supported\n");
|
|
}
|
|
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return ret;
|
|
}
|
|
|
|
static u32 beiscsi_get_post_stage(struct beiscsi_hba *phba)
|
|
{
|
|
u32 sem;
|
|
|
|
if (is_chip_be2_be3r(phba))
|
|
sem = ioread32(phba->csr_va + SLIPORT_SEMAPHORE_OFFSET_BEx);
|
|
else
|
|
pci_read_config_dword(phba->pcidev,
|
|
SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
|
|
return sem;
|
|
}
|
|
|
|
int beiscsi_check_fw_rdy(struct beiscsi_hba *phba)
|
|
{
|
|
u32 loop, post, rdy = 0;
|
|
|
|
loop = 1000;
|
|
while (loop--) {
|
|
post = beiscsi_get_post_stage(phba);
|
|
if (post & POST_ERROR_BIT)
|
|
break;
|
|
if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) {
|
|
rdy = 1;
|
|
break;
|
|
}
|
|
msleep(60);
|
|
}
|
|
|
|
if (!rdy) {
|
|
__beiscsi_log(phba, KERN_ERR,
|
|
"BC_%d : FW not ready 0x%x\n", post);
|
|
}
|
|
|
|
return rdy;
|
|
}
|
|
|
|
int beiscsi_cmd_function_reset(struct beiscsi_hba *phba)
|
|
{
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_post_sgl_pages_req *req;
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
|
|
req = embedded_payload(wrb);
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
|
|
status = be_mbox_notify(ctrl);
|
|
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
|
|
u8 *endian_check;
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
endian_check = (u8 *) wrb;
|
|
if (load) {
|
|
/* to start communicating */
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0x12;
|
|
*endian_check++ = 0x34;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0x56;
|
|
*endian_check++ = 0x78;
|
|
*endian_check++ = 0xFF;
|
|
} else {
|
|
/* to stop communicating */
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xAA;
|
|
*endian_check++ = 0xBB;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xFF;
|
|
*endian_check++ = 0xCC;
|
|
*endian_check++ = 0xDD;
|
|
*endian_check = 0xFF;
|
|
}
|
|
be_dws_cpu_to_le(wrb, sizeof(*wrb));
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (status)
|
|
beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
|
|
"BC_%d : special WRB message failed\n");
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int beiscsi_init_sliport(struct beiscsi_hba *phba)
|
|
{
|
|
int status;
|
|
|
|
/* check POST stage before talking to FW */
|
|
status = beiscsi_check_fw_rdy(phba);
|
|
if (!status)
|
|
return -EIO;
|
|
|
|
/* clear all error states after checking FW rdy */
|
|
phba->state &= ~BEISCSI_HBA_IN_ERR;
|
|
|
|
/* check again UER support */
|
|
phba->state &= ~BEISCSI_HBA_UER_SUPP;
|
|
|
|
/*
|
|
* SLI COMMON_FUNCTION_RESET completion is indicated by BMBX RDY bit.
|
|
* It should clean up any stale info in FW for this fn.
|
|
*/
|
|
status = beiscsi_cmd_function_reset(phba);
|
|
if (status) {
|
|
beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
|
|
"BC_%d : SLI Function Reset failed\n");
|
|
return status;
|
|
}
|
|
|
|
/* indicate driver is loading */
|
|
return beiscsi_cmd_special_wrb(&phba->ctrl, 1);
|
|
}
|
|
|
|
/**
|
|
* beiscsi_cmd_iscsi_cleanup()- Inform FW to cleanup EP data structures.
|
|
* @phba: pointer to dev priv structure
|
|
* @ulp: ULP number.
|
|
*
|
|
* return
|
|
* Success: 0
|
|
* Failure: Non-Zero Value
|
|
**/
|
|
int beiscsi_cmd_iscsi_cleanup(struct beiscsi_hba *phba, unsigned short ulp)
|
|
{
|
|
struct be_ctrl_info *ctrl = &phba->ctrl;
|
|
struct iscsi_cleanup_req_v1 *req_v1;
|
|
struct iscsi_cleanup_req *req;
|
|
u16 hdr_ring_id, data_ring_id;
|
|
struct be_mcc_wrb *wrb;
|
|
int status;
|
|
|
|
mutex_lock(&ctrl->mbox_lock);
|
|
wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
|
|
hdr_ring_id = HWI_GET_DEF_HDRQ_ID(phba, ulp);
|
|
data_ring_id = HWI_GET_DEF_BUFQ_ID(phba, ulp);
|
|
if (is_chip_be2_be3r(phba)) {
|
|
req = embedded_payload(wrb);
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_CLEANUP, sizeof(*req));
|
|
req->chute = (1 << ulp);
|
|
/* BE2/BE3 FW creates 8-bit ring id */
|
|
req->hdr_ring_id = hdr_ring_id;
|
|
req->data_ring_id = data_ring_id;
|
|
} else {
|
|
req_v1 = embedded_payload(wrb);
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req_v1), true, 0);
|
|
be_cmd_hdr_prepare(&req_v1->hdr, CMD_SUBSYSTEM_ISCSI,
|
|
OPCODE_COMMON_ISCSI_CLEANUP,
|
|
sizeof(*req_v1));
|
|
req_v1->hdr.version = 1;
|
|
req_v1->chute = (1 << ulp);
|
|
req_v1->hdr_ring_id = cpu_to_le16(hdr_ring_id);
|
|
req_v1->data_ring_id = cpu_to_le16(data_ring_id);
|
|
}
|
|
|
|
status = be_mbox_notify(ctrl);
|
|
if (status)
|
|
beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
|
|
"BG_%d : %s failed %d\n", __func__, ulp);
|
|
mutex_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* beiscsi_detect_ue()- Detect Unrecoverable Error on adapter
|
|
* @phba: Driver priv structure
|
|
*
|
|
* Read registers linked to UE and check for the UE status
|
|
**/
|
|
int beiscsi_detect_ue(struct beiscsi_hba *phba)
|
|
{
|
|
uint32_t ue_mask_hi = 0, ue_mask_lo = 0;
|
|
uint32_t ue_hi = 0, ue_lo = 0;
|
|
uint8_t i = 0;
|
|
int ret = 0;
|
|
|
|
pci_read_config_dword(phba->pcidev,
|
|
PCICFG_UE_STATUS_LOW, &ue_lo);
|
|
pci_read_config_dword(phba->pcidev,
|
|
PCICFG_UE_STATUS_MASK_LOW,
|
|
&ue_mask_lo);
|
|
pci_read_config_dword(phba->pcidev,
|
|
PCICFG_UE_STATUS_HIGH,
|
|
&ue_hi);
|
|
pci_read_config_dword(phba->pcidev,
|
|
PCICFG_UE_STATUS_MASK_HI,
|
|
&ue_mask_hi);
|
|
|
|
ue_lo = (ue_lo & ~ue_mask_lo);
|
|
ue_hi = (ue_hi & ~ue_mask_hi);
|
|
|
|
|
|
if (ue_lo || ue_hi) {
|
|
set_bit(BEISCSI_HBA_IN_UE, &phba->state);
|
|
__beiscsi_log(phba, KERN_ERR,
|
|
"BC_%d : HBA error detected\n");
|
|
ret = 1;
|
|
}
|
|
|
|
if (ue_lo) {
|
|
for (i = 0; ue_lo; ue_lo >>= 1, i++) {
|
|
if (ue_lo & 1)
|
|
__beiscsi_log(phba, KERN_ERR,
|
|
"BC_%d : UE_LOW %s bit set\n",
|
|
desc_ue_status_low[i]);
|
|
}
|
|
}
|
|
|
|
if (ue_hi) {
|
|
for (i = 0; ue_hi; ue_hi >>= 1, i++) {
|
|
if (ue_hi & 1)
|
|
__beiscsi_log(phba, KERN_ERR,
|
|
"BC_%d : UE_HIGH %s bit set\n",
|
|
desc_ue_status_hi[i]);
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* beiscsi_detect_tpe()- Detect Transient Parity Error on adapter
|
|
* @phba: Driver priv structure
|
|
*
|
|
* Read SLIPORT SEMAPHORE register to check for UER
|
|
*
|
|
**/
|
|
int beiscsi_detect_tpe(struct beiscsi_hba *phba)
|
|
{
|
|
u32 post, status;
|
|
int ret = 0;
|
|
|
|
post = beiscsi_get_post_stage(phba);
|
|
status = post & POST_STAGE_MASK;
|
|
if ((status & POST_ERR_RECOVERY_CODE_MASK) ==
|
|
POST_STAGE_RECOVERABLE_ERR) {
|
|
set_bit(BEISCSI_HBA_IN_TPE, &phba->state);
|
|
__beiscsi_log(phba, KERN_INFO,
|
|
"BC_%d : HBA error recoverable: 0x%x\n", post);
|
|
ret = 1;
|
|
} else {
|
|
__beiscsi_log(phba, KERN_INFO,
|
|
"BC_%d : HBA in UE: 0x%x\n", post);
|
|
}
|
|
|
|
return ret;
|
|
}
|