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5db568e748
If a Cortex-A715 cpu sees a page mapping permissions change from executable to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers, on the next instruction abort caused by permission fault. Only user-space does executable to non-executable permission transition via mprotect() system call which calls ptep_modify_prot_start() and ptep_modify _prot_commit() helpers, while changing the page mapping. The platform code can override these helpers via __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION. Work around the problem via doing a break-before-make TLB invalidation, for all executable user space mappings, that go through mprotect() system call. This overrides ptep_modify_prot_start() and ptep_modify_prot_commit(), via defining HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION on the platform thus giving an opportunity to intercept user space exec mappings, and do the necessary TLB invalidation. Similar interceptions are also implemented for HugeTLB. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20230102061651.34745-1-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
90 lines
1.6 KiB
Plaintext
90 lines
1.6 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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#
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# Internal CPU capabilities constants, keep this list sorted
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ALWAYS_BOOT
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ALWAYS_SYSTEM
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BTI
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# Unreliable: use system_supports_32bit_el0() instead.
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HAS_32BIT_EL0_DO_NOT_USE
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HAS_32BIT_EL1
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HAS_ADDRESS_AUTH
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HAS_ADDRESS_AUTH_ARCH_QARMA3
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HAS_ADDRESS_AUTH_ARCH_QARMA5
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HAS_ADDRESS_AUTH_IMP_DEF
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HAS_AMU_EXTN
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HAS_ARMv8_4_TTL
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HAS_CACHE_DIC
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HAS_CACHE_IDC
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HAS_CNP
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HAS_CRC32
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HAS_DCPODP
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HAS_DCPOP
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HAS_DIT
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HAS_E0PD
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HAS_ECV
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HAS_EPAN
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HAS_GENERIC_AUTH
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HAS_GENERIC_AUTH_ARCH_QARMA3
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HAS_GENERIC_AUTH_ARCH_QARMA5
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HAS_GENERIC_AUTH_IMP_DEF
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HAS_IRQ_PRIO_MASKING
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HAS_LDAPR
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HAS_LSE_ATOMICS
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HAS_NO_FPSIMD
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HAS_NO_HW_PREFETCH
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HAS_PAN
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HAS_RAS_EXTN
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HAS_RNG
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HAS_SB
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HAS_STAGE2_FWB
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HAS_SYSREG_GIC_CPUIF
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HAS_TIDCP1
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HAS_TLB_RANGE
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HAS_VIRT_HOST_EXTN
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HAS_WFXT
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HW_DBM
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KVM_PROTECTED_MODE
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MISMATCHED_CACHE_TYPE
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MTE
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MTE_ASYMM
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SME
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SME_FA64
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SPECTRE_V2
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SPECTRE_V3A
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SPECTRE_V4
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SPECTRE_BHB
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SSBS
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SVE
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UNMAP_KERNEL_AT_EL0
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WORKAROUND_834220
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WORKAROUND_843419
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WORKAROUND_845719
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WORKAROUND_858921
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WORKAROUND_1418040
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WORKAROUND_1463225
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WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_1742098
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WORKAROUND_1902691
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WORKAROUND_2038923
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WORKAROUND_2064142
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WORKAROUND_2077057
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WORKAROUND_2457168
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WORKAROUND_2645198
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WORKAROUND_2658417
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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WORKAROUND_CAVIUM_23154
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WORKAROUND_CAVIUM_27456
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WORKAROUND_CAVIUM_30115
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WORKAROUND_CAVIUM_TX2_219_PRFM
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WORKAROUND_CAVIUM_TX2_219_TVM
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WORKAROUND_CLEAN_CACHE
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WORKAROUND_DEVICE_LOAD_ACQUIRE
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WORKAROUND_NVIDIA_CARMEL_CNP
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WORKAROUND_QCOM_FALKOR_E1003
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WORKAROUND_REPEAT_TLBI
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WORKAROUND_SPECULATIVE_AT
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