linux/drivers/base
Linus Torvalds 4527e83780 Updates for the MSI interrupt subsystem and RISC-V initial MSI support:
- Core and platform-MSI
 
     The core changes have been adopted from previous work which converted
     ARM[64] to the new per device MSI domain model, which was merged to
     support multiple MSI domain per device. The ARM[64] changes are being
     worked on too, but have not been ready yet. The core and platform-MSI
     changes have been split out to not hold up RISC-V and to avoid that
     RISC-V builds on the scheduled for removal interfaces.
 
     The core support provides new interfaces to handle wire to MSI bridges
     in a straight forward way and introduces new platform-MSI interfaces
     which are built on top of the per device MSI domain model.
 
     Once ARM[64] is converted over the old platform-MSI interfaces and the
     related ugliness in the MSI core code will be removed.
 
   - Drivers:
 
     - Add a new driver for the Andes hart-level interrupt controller
 
     - Rework the SiFive PLIC driver to prepare for MSI suport
 
     - Expand the RISC-V INTC driver to support the new RISC-V AIA
       controller which provides the basis for MSI on RISC-V
 
     - A few fixup for the fallout of the core changes.
 
     The actual MSI parts for RISC-V were finalized late and have been
     post-poned for the next merge window.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmXt7MsTHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYofrMD/9Dag12ttmbE2uqzTzlTxc7RHC2MX5n
 VJLt84FNNwGPA4r7WLOOqHrfuvfoGjuWT9pYMrVaXCglRG1CMvL10kHMB2f28UWv
 Qpc5PzbJwpD6tqyfRSFHMoJp63DAI8IpS7J3I8bqnRD8+0PwYn3jMA1+iMZkH0B7
 8uO3mxlFhQ7BFvIAeMEAhR0szuAfvXqEtpi1iTgQTrQ4Je4Rf1pmLjEe2rkwDvF4
 p3SAmPIh4+F3IjO7vNsVkQ2yOarTP2cpSns6JmO8mrobLIVX7ZCQ6uVaVCfBhxfx
 WttuJO6Bmh/I15yDe/waH6q9ym+0VBwYRWi5lonMpViGdq4/D2WVnY1mNeLRIfjl
 X65aMWE1+bhiqyIIUfc24hacf0UgBIlMEW4kJ31VmQzb+OyLDXw+UvzWg1dO6XdA
 3L6j1nRgHk0ea5yFyH6SfH/mrfeyqHuwHqo17KFyHxD3jM2H1RRMplpbwXiOIepp
 KJJ/O06eMEzHqzn4B8GCT2EvX6L2ehgoWbLeEDNLQh/3LwA9OdcBzPr6gsweEl0U
 Q7szJgUWZHeMr39F2rnt0GmvkEuu6muEp/nQzfnohjoYZ0PhpMLSq++4Gi+Ko3fz
 2IyecJ+tlbSfyM5//8AdNnOSpsTG3f8u6B/WwhGp5lIDwMnMzCssgfQmRnc3Uyv5
 kU3pdMjURJaTUA==
 =7aXj
 -----END PGP SIGNATURE-----

Merge tag 'irq-msi-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull MSI updates from Thomas Gleixner:
 "Updates for the MSI interrupt subsystem and initial RISC-V MSI
  support.

  The core changes have been adopted from previous work which converted
  ARM[64] to the new per device MSI domain model, which was merged to
  support multiple MSI domain per device. The ARM[64] changes are being
  worked on too, but have not been ready yet. The core and platform-MSI
  changes have been split out to not hold up RISC-V and to avoid that
  RISC-V builds on the scheduled for removal interfaces.

  The core support provides new interfaces to handle wire to MSI bridges
  in a straight forward way and introduces new platform-MSI interfaces
  which are built on top of the per device MSI domain model.

  Once ARM[64] is converted over the old platform-MSI interfaces and the
  related ugliness in the MSI core code will be removed.

  The actual MSI parts for RISC-V were finalized late and have been
  post-poned for the next merge window.

  Drivers:

   - Add a new driver for the Andes hart-level interrupt controller

   - Rework the SiFive PLIC driver to prepare for MSI suport

   - Expand the RISC-V INTC driver to support the new RISC-V AIA
     controller which provides the basis for MSI on RISC-V

   - A few fixup for the fallout of the core changes"

* tag 'irq-msi-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (29 commits)
  irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA
  x86/apic/msi: Use DOMAIN_BUS_GENERIC_MSI for HPET/IO-APIC domain search
  genirq/matrix: Dynamic bitmap allocation
  irqchip/riscv-intc: Add support for RISC-V AIA
  irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore
  irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_probe()
  irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure
  irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode
  irqchip/sifive-plic: Use devm_xyz() for managed allocation
  irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()
  irqchip/sifive-plic: Convert PLIC driver into a platform driver
  irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  irqchip/riscv-intc: Allow large non-standard interrupt number
  genirq/irqdomain: Don't call ops->select for DOMAIN_BUS_ANY tokens
  irqchip/imx-intmux: Handle pure domain searches correctly
  genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV
  genirq/irqdomain: Reroute device MSI create_mapping
  genirq/msi: Provide allocation/free functions for "wired" MSI interrupts
  genirq/msi: Optionally use dev->fwnode for device domain
  genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI
  ...
2024-03-11 14:03:03 -07:00
..
firmware_loader firmware_loader: Expand Firmware upload error codes with firmware invalid error 2023-11-24 18:09:19 -08:00
power RTC for 6.8 2024-01-18 17:25:39 -08:00
regmap regmap: kunit: Ensure that changed bytes are actually different 2024-02-12 13:55:51 +00:00
test drivers: base: test: Make property entry API test modular 2023-10-05 13:11:44 +02:00
arch_numa.c arm64: irq: set the correct node for VMAP stack 2023-12-05 14:26:50 +00:00
arch_topology.c topology: Set capacity_freq_ref in all cases 2024-01-30 16:01:22 -08:00
attribute_container.c
auxiliary.c driver core: mark remaining local bus_type variables as const 2023-12-21 13:56:30 +01:00
base.h block: make block_class constant 2024-03-06 08:29:20 -07:00
bus.c driver core: bus: constantify subsys_register() calls 2023-12-21 13:55:38 +01:00
cacheinfo.c mm, pcp: reduce lock contention for draining high-order pages 2023-10-25 16:47:10 -07:00
class.c class: fix use-after-free in class_register() 2024-01-04 17:13:04 +01:00
component.c drivers: base: component: fix memory leak with using debugfs_lookup() 2023-02-08 13:33:10 +01:00
container.c driver core: container: make container_subsys const 2023-12-21 13:56:10 +01:00
core.c driver core: fw_devlink: Improve logs for cycle detection 2024-02-02 07:12:33 -08:00
cpu.c Driver core changes for 6.8-rc1 2024-01-18 09:48:40 -08:00
dd.c driver core: Emit reason for pending deferred probe 2023-12-07 11:35:26 +09:00
devcoredump.c devcoredump: Send uevent once devcd is ready 2023-11-28 19:39:18 +00:00
devres.c drivers/base: use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN 2023-06-19 16:19:20 -07:00
devtmpfs.c driver core: clean up the logic to determine which /sys/dev/ directory to use 2023-03-31 17:45:07 +02:00
driver.c driver core: create bus_is_registered() 2023-02-09 10:43:35 +01:00
firmware.c
hypervisor.c
init.c drivers: base: Move cpu_dev_init() after node_dev_init() 2023-12-06 12:41:49 +09:00
isa.c driver core: mark remaining local bus_type variables as const 2023-12-21 13:56:30 +01:00
Kconfig driver core: Add CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT 2023-03-28 18:45:59 +02:00
Makefile
map.c
memory.c Driver core changes for 6.8-rc1 2024-01-18 09:48:40 -08:00
module.c
node.c cxl for v6.8 2024-01-18 16:22:43 -08:00
physical_location.c driver core: location: Free struct acpi_pld_info *pld before return false 2023-01-20 14:20:30 +01:00
physical_location.h driver core: physical_location.h remove extern from function prototypes 2023-03-24 15:35:48 +01:00
pinctrl.c
platform-msi.c platform-msi: Remove unused interfaces 2024-02-15 17:55:40 +01:00
platform.c driver core: platform: Annotate struct irq_affinity_devres with __counted_by 2023-10-07 18:13:09 +02:00
property.c Driver core changes for 6.8-rc1 2024-01-18 09:48:40 -08:00
soc.c driver core: mark remaining local bus_type variables as const 2023-12-21 13:56:30 +01:00
swnode.c software node: Let args be NULL in software_node_get_reference_args 2023-12-07 11:35:26 +09:00
syscore.c
topology.c
trace.c
trace.h
transport_class.c drivers: base: transport_class: fix resource leak when transport_add_device() fails 2023-01-20 14:22:53 +01:00