mirror of
https://github.com/torvalds/linux.git
synced 2024-11-19 10:31:48 +00:00
b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
311 lines
10 KiB
C
311 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
|
|
*
|
|
* Copyright (C) 2000 Geert Uytterhoeven <geert@linux-m68k.org>
|
|
* Sony Software Development Center Europe (SDCE), Brussels
|
|
*
|
|
* This file is based on the following documentation:
|
|
*
|
|
* NEC Vrc 5074 System Controller Data Sheet, June 1998
|
|
*/
|
|
|
|
#ifndef _ASM_NILE4_H
|
|
#define _ASM_NILE4_H
|
|
|
|
#define NILE4_BASE 0xbfa00000
|
|
#define NILE4_SIZE 0x00200000 /* 2 MB */
|
|
|
|
|
|
/*
|
|
* Physical Device Address Registers (PDARs)
|
|
*/
|
|
|
|
#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
|
|
#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
|
|
#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
|
|
#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
|
|
#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
|
|
#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
|
|
#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
|
|
#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
|
|
#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
|
|
#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
|
|
#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
|
|
#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */
|
|
/* [R/W] */
|
|
#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
|
|
|
|
|
|
/*
|
|
* CPU Interface Registers
|
|
*/
|
|
|
|
#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */
|
|
#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */
|
|
#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
|
|
#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
|
|
/* Enable [R/W] */
|
|
#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
|
|
#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
|
|
|
|
|
|
/*
|
|
* Memory-Interface Registers
|
|
*/
|
|
|
|
#define NILE4_MEMCTRL 0x00C0 /* Memory Control */
|
|
#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
|
|
#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
|
|
|
|
|
|
/*
|
|
* PCI-Bus Registers
|
|
*/
|
|
|
|
#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
|
|
#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
|
|
#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
|
|
#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
|
|
#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
|
|
|
|
|
|
/*
|
|
* Local-Bus Registers
|
|
*/
|
|
|
|
#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
|
|
#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
|
|
#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
|
|
#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
|
|
#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
|
|
#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
|
|
#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
|
|
#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
|
|
#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
|
|
/* Enables [R/W] */
|
|
#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
|
|
#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
|
|
|
|
|
|
/*
|
|
* DMA Registers
|
|
*/
|
|
|
|
#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
|
|
#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
|
|
#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
|
|
#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
|
|
#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
|
|
#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
|
|
|
|
|
|
/*
|
|
* Timer Registers
|
|
*/
|
|
|
|
#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
|
|
#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
|
|
#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
|
|
#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
|
|
#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
|
|
#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
|
|
#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
|
|
#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
|
|
|
|
|
|
/*
|
|
* PCI Configuration Space Registers
|
|
*/
|
|
|
|
#define NILE4_PCI_BASE 0x0200
|
|
|
|
#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
|
|
#define NILE4_DID 0x0202 /* PCI Device ID [R] */
|
|
#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
|
|
#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
|
|
#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
|
|
#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
|
|
#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
|
|
#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
|
|
#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
|
|
#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */
|
|
#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
|
|
#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
|
|
#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
|
|
#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
|
|
/* (unimplemented) */
|
|
#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
|
|
#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
|
|
#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
|
|
/* (unimplemented) */
|
|
#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
|
|
#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
|
|
#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
|
|
#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
|
|
#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
|
|
#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
|
|
#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
|
|
#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
|
|
#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
|
|
#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
|
|
#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
|
|
#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
|
|
|
|
|
|
/*
|
|
* Serial-Port Registers
|
|
*/
|
|
|
|
#define NILE4_UART_BASE 0x0300
|
|
|
|
#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */
|
|
#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */
|
|
#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */
|
|
#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */
|
|
#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */
|
|
#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */
|
|
#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */
|
|
#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */
|
|
#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */
|
|
#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */
|
|
#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */
|
|
#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */
|
|
|
|
#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */
|
|
|
|
|
|
/*
|
|
* Interrupt Lines
|
|
*/
|
|
|
|
#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */
|
|
#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */
|
|
#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
|
|
#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */
|
|
#define NILE4_INT_UART 4 /* UART Interrupt */
|
|
#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */
|
|
#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */
|
|
#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */
|
|
#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
|
|
#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
|
|
#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
|
|
#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
|
|
#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
|
|
#define NILE4_INT_RESV 13 /* Reserved */
|
|
#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
|
|
#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
|
|
|
|
|
|
/*
|
|
* Nile 4 Register Access
|
|
*/
|
|
|
|
static inline void nile4_sync(void)
|
|
{
|
|
volatile u32 *p = (volatile u32 *)0xbfc00000;
|
|
(void)(*p);
|
|
}
|
|
|
|
static inline void nile4_out32(u32 offset, u32 val)
|
|
{
|
|
*(volatile u32 *)(NILE4_BASE+offset) = val;
|
|
nile4_sync();
|
|
}
|
|
|
|
static inline u32 nile4_in32(u32 offset)
|
|
{
|
|
u32 val = *(volatile u32 *)(NILE4_BASE+offset);
|
|
nile4_sync();
|
|
return val;
|
|
}
|
|
|
|
static inline void nile4_out16(u32 offset, u16 val)
|
|
{
|
|
*(volatile u16 *)(NILE4_BASE+offset) = val;
|
|
nile4_sync();
|
|
}
|
|
|
|
static inline u16 nile4_in16(u32 offset)
|
|
{
|
|
u16 val = *(volatile u16 *)(NILE4_BASE+offset);
|
|
nile4_sync();
|
|
return val;
|
|
}
|
|
|
|
static inline void nile4_out8(u32 offset, u8 val)
|
|
{
|
|
*(volatile u8 *)(NILE4_BASE+offset) = val;
|
|
nile4_sync();
|
|
}
|
|
|
|
static inline u8 nile4_in8(u32 offset)
|
|
{
|
|
u8 val = *(volatile u8 *)(NILE4_BASE+offset);
|
|
nile4_sync();
|
|
return val;
|
|
}
|
|
|
|
|
|
/*
|
|
* Physical Device Address Registers
|
|
*/
|
|
|
|
extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
|
|
int on_memory_bus, int visible);
|
|
|
|
|
|
/*
|
|
* PCI Master Registers
|
|
*/
|
|
|
|
#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
|
|
#define NILE4_PCICMD_IO 1 /* PCI I/O Space */
|
|
#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
|
|
#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
|
|
|
|
|
|
/*
|
|
* PCI Address Spaces
|
|
*
|
|
* Note that these are multiplexed using PCIINIT[01]!
|
|
*/
|
|
|
|
#define NILE4_PCI_IO_BASE 0xa6000000
|
|
#define NILE4_PCI_MEM_BASE 0xa8000000
|
|
#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
|
|
#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
|
|
|
|
|
|
extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
|
|
|
|
|
|
/*
|
|
* Interrupt Programming
|
|
*/
|
|
|
|
#define NUM_I8259_INTERRUPTS 16
|
|
#define NUM_NILE4_INTERRUPTS 16
|
|
|
|
#define IRQ_I8259_CASCADE NILE4_INT_INTE
|
|
#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
|
|
#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
|
|
#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
|
|
|
|
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
|
|
extern void nile4_map_irq_all(int cpu_irq);
|
|
extern void nile4_enable_irq(unsigned int nile4_irq);
|
|
extern void nile4_disable_irq(unsigned int nile4_irq);
|
|
extern void nile4_disable_irq_all(void);
|
|
extern u16 nile4_get_irq_stat(int cpu_irq);
|
|
extern void nile4_enable_irq_output(int cpu_irq);
|
|
extern void nile4_disable_irq_output(int cpu_irq);
|
|
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
|
|
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
|
|
extern void nile4_clear_irq(int nile4_irq);
|
|
extern void nile4_clear_irq_mask(u32 mask);
|
|
extern u8 nile4_i8259_iack(void);
|
|
extern void nile4_dump_irq_status(void); /* Debug */
|
|
|
|
#endif
|