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bc3ec75de5
All the cache maintainance is already stubbed out when not enabled, but merging the two allows us to nicely handle the case where cache maintainance is required for some devices, but not others. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Paul Burton <paul.burton@mips.com> # MIPS parts
31 lines
703 B
C
31 lines
703 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_DMA_MAPPING_H
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#define _ASM_DMA_MAPPING_H
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#include <linux/swiotlb.h>
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extern const struct dma_map_ops jazz_dma_ops;
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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{
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#if defined(CONFIG_MACH_JAZZ)
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return &jazz_dma_ops;
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#elif defined(CONFIG_SWIOTLB)
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return &swiotlb_dma_ops;
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#else
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return &dma_direct_ops;
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#endif
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}
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#define arch_setup_dma_ops arch_setup_dma_ops
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static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
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u64 size, const struct iommu_ops *iommu,
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bool coherent)
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{
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#ifdef CONFIG_DMA_PERDEV_COHERENT
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dev->dma_coherent = coherent;
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#endif
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}
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#endif /* _ASM_DMA_MAPPING_H */
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