Chunyan Zhang 3e37b00558 clk: sprd: add adjustable pll support ... Introduced a common adjustable pll clock driver for Spreadtrum SoCs. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-12-21 15:00:53 -08:00
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common.c
common.h
composite.c	clk: sprd: add composite clock support	2017-12-21 15:00:52 -08:00
composite.h	clk: sprd: add composite clock support	2017-12-21 15:00:52 -08:00
div.c	clk: sprd: add divider clock support	2017-12-21 15:00:52 -08:00
div.h	clk: sprd: add divider clock support	2017-12-21 15:00:52 -08:00
gate.c
gate.h
Kconfig
Makefile	clk: sprd: add adjustable pll support	2017-12-21 15:00:53 -08:00
mux.c	clk: sprd: add mux clock support	2017-12-21 15:00:52 -08:00
mux.h	clk: sprd: add mux clock support	2017-12-21 15:00:52 -08:00
pll.c	clk: sprd: add adjustable pll support	2017-12-21 15:00:53 -08:00
pll.h	clk: sprd: add adjustable pll support	2017-12-21 15:00:53 -08:00