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get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
128 lines
3.2 KiB
ArmAsm
128 lines
3.2 KiB
ArmAsm
/*
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* include/asm-arm/arch-pnx4008/entry-macro.S
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*
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* Low-level IRQ helper macros for PNX4008-based platforms
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*
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* 2005-2006 (c) MontaVista Software, Inc.
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* Author: Vitaly Wool <vwool@ru.mvista.com>
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "platform.h"
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#define IO_BASE 0xF0000000
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#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
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#define INTRC_MASK 0x00
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#define INTRC_RAW_STAT 0x04
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#define INTRC_STAT 0x08
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#define INTRC_POLAR 0x0C
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#define INTRC_ACT_TYPE 0x10
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#define INTRC_TYPE 0x14
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#define SIC1_BASE_INT 32
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#define SIC2_BASE_INT 64
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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/* decode the MIC interrupt numbers */
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ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
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ldr \irqstat, [\base, #INTRC_STAT]
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cmp \irqstat,#1<<16
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movhs \irqnr,#16
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movlo \irqnr,#0
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movhs \irqstat,\irqstat,lsr#16
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cmp \irqstat,#1<<8
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addhs \irqnr,\irqnr,#8
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movhs \irqstat,\irqstat,lsr#8
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cmp \irqstat,#1<<4
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addhs \irqnr,\irqnr,#4
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movhs \irqstat,\irqstat,lsr#4
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cmp \irqstat,#1<<2
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addhs \irqnr,\irqnr,#2
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movhs \irqstat,\irqstat,lsr#2
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cmp \irqstat,#1<<1
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addhs \irqnr,\irqnr,#1
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/* was there an interrupt ? if not then drop out with EQ status */
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teq \irqstat,#0
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beq 1003f
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/* and now check for extended IRQ reasons */
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cmp \irqnr,#1
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bls 1003f
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cmp \irqnr,#30
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blo 1002f
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/* IRQ 31,30 : High priority cascade IRQ handle */
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/* read the correct SIC */
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/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
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/* set the base IRQ number */
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ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
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moveq \irqnr,#SIC1_BASE_INT
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ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
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movne \irqnr,#SIC2_BASE_INT
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ldr \irqstat, [\base, #INTRC_STAT]
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ldr \tmp, [\base, #INTRC_TYPE]
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/* and with inverted mask : low priority interrupts */
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and \irqstat,\irqstat,\tmp
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b 1004f
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1003:
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/* IRQ 1,0 : Low priority cascade IRQ handle */
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/* read the correct SIC */
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/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
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/* read the correct SIC */
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/* set the base IRQ number */
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ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
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movne \irqnr,#SIC1_BASE_INT
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ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
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moveq \irqnr,#SIC2_BASE_INT
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ldr \irqstat, [\base, #INTRC_STAT]
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ldr \tmp, [\base, #INTRC_TYPE]
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/* and with inverted mask : low priority interrupts */
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bic \irqstat,\irqstat,\tmp
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1004:
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cmp \irqstat,#1<<16
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addhs \irqnr,\irqnr,#16
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movhs \irqstat,\irqstat,lsr#16
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cmp \irqstat,#1<<8
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addhs \irqnr,\irqnr,#8
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movhs \irqstat,\irqstat,lsr#8
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cmp \irqstat,#1<<4
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addhs \irqnr,\irqnr,#4
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movhs \irqstat,\irqstat,lsr#4
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cmp \irqstat,#1<<2
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addhs \irqnr,\irqnr,#2
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movhs \irqstat,\irqstat,lsr#2
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cmp \irqstat,#1<<1
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addhs \irqnr,\irqnr,#1
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/* is irqstat not zero */
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1002:
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/* we assert that irqstat is not equal to zero and return ne status if true*/
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teq \irqstat,#0
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1003:
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.endm
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.macro irq_prio_table
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.endm
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