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84dacb9cad
DRM driver get the comp->clk by of_clk_get(), we only assign NULL to comp->clk when error happened, but do not return the error number. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
343 lines
9.6 KiB
C
343 lines
9.6 KiB
C
/*
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* Copyright (c) 2015 MediaTek Inc.
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* Authors:
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* YT Shen <yt.shen@mediatek.com>
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* CK Hu <ck.hu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <drm/drmP.h>
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#include "mtk_drm_drv.h"
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#include "mtk_drm_plane.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_crtc.h"
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#define DISP_OD_EN 0x0000
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#define DISP_OD_INTEN 0x0008
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#define DISP_OD_INTSTA 0x000c
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#define DISP_OD_CFG 0x0020
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#define DISP_OD_SIZE 0x0030
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#define DISP_DITHER_5 0x0114
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#define DISP_DITHER_7 0x011c
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#define DISP_DITHER_15 0x013c
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#define DISP_DITHER_16 0x0140
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#define DISP_REG_UFO_START 0x0000
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#define DISP_AAL_EN 0x0000
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#define DISP_AAL_SIZE 0x0030
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#define DISP_GAMMA_EN 0x0000
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#define DISP_GAMMA_CFG 0x0020
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#define DISP_GAMMA_SIZE 0x0030
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#define DISP_GAMMA_LUT 0x0700
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#define LUT_10BIT_MASK 0x03ff
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#define OD_RELAYMODE BIT(0)
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#define UFO_BYPASS BIT(2)
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#define AAL_EN BIT(0)
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#define GAMMA_EN BIT(0)
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#define GAMMA_LUT_EN BIT(1)
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#define DISP_DITHERING BIT(2)
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#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
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#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
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#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
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#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
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#define DITHER_NEW_BIT_MODE BIT(0)
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#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
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#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
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#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
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#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
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#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
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#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
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#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
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#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
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void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
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unsigned int CFG)
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{
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/* If bpc equal to 0, the dithering function didn't be enabled */
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if (bpc == 0)
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return;
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if (bpc >= MTK_MIN_BPC) {
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writel(0, comp->regs + DISP_DITHER_5);
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writel(0, comp->regs + DISP_DITHER_7);
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writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
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DITHER_NEW_BIT_MODE,
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comp->regs + DISP_DITHER_15);
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writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
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DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
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comp->regs + DISP_DITHER_16);
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writel(DISP_DITHERING, comp->regs + CFG);
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}
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}
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static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
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writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
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mtk_dither_set(comp, bpc, DISP_OD_CFG);
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}
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static void mtk_od_start(struct mtk_ddp_comp *comp)
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{
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writel(1, comp->regs + DISP_OD_EN);
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}
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static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
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{
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writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
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}
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static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
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}
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static void mtk_aal_start(struct mtk_ddp_comp *comp)
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{
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writel(AAL_EN, comp->regs + DISP_AAL_EN);
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}
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static void mtk_aal_stop(struct mtk_ddp_comp *comp)
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{
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writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
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}
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static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
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mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
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}
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static void mtk_gamma_start(struct mtk_ddp_comp *comp)
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{
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writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN);
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}
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static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
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{
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writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
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}
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static void mtk_gamma_set(struct mtk_ddp_comp *comp,
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struct drm_crtc_state *state)
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{
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unsigned int i, reg;
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struct drm_color_lut *lut;
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void __iomem *lut_base;
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u32 word;
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if (state->gamma_lut) {
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reg = readl(comp->regs + DISP_GAMMA_CFG);
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reg = reg | GAMMA_LUT_EN;
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writel(reg, comp->regs + DISP_GAMMA_CFG);
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lut_base = comp->regs + DISP_GAMMA_LUT;
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lut = (struct drm_color_lut *)state->gamma_lut->data;
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for (i = 0; i < MTK_LUT_SIZE; i++) {
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word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
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(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
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((lut[i].blue >> 6) & LUT_10BIT_MASK);
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writel(word, (lut_base + i * 4));
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}
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}
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}
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static const struct mtk_ddp_comp_funcs ddp_aal = {
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.gamma_set = mtk_gamma_set,
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.config = mtk_aal_config,
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.start = mtk_aal_start,
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.stop = mtk_aal_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_gamma = {
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.gamma_set = mtk_gamma_set,
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.config = mtk_gamma_config,
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.start = mtk_gamma_start,
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.stop = mtk_gamma_stop,
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};
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static const struct mtk_ddp_comp_funcs ddp_od = {
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.config = mtk_od_config,
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.start = mtk_od_start,
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};
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static const struct mtk_ddp_comp_funcs ddp_ufoe = {
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.start = mtk_ufoe_start,
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};
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static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
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[MTK_DISP_OVL] = "ovl",
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[MTK_DISP_RDMA] = "rdma",
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[MTK_DISP_WDMA] = "wdma",
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[MTK_DISP_COLOR] = "color",
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[MTK_DISP_AAL] = "aal",
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[MTK_DISP_GAMMA] = "gamma",
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[MTK_DISP_UFOE] = "ufoe",
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[MTK_DSI] = "dsi",
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[MTK_DPI] = "dpi",
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[MTK_DISP_PWM] = "pwm",
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[MTK_DISP_MUTEX] = "mutex",
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[MTK_DISP_OD] = "od",
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[MTK_DISP_BLS] = "bls",
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};
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struct mtk_ddp_comp_match {
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enum mtk_ddp_comp_type type;
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int alias_id;
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const struct mtk_ddp_comp_funcs *funcs;
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};
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static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
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[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
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[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
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[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
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[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
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[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
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[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL },
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[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
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[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
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[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL },
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[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL },
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[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
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[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
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[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
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[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
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[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
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[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
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[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
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[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
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[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
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[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
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[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
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[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
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[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
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[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
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};
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int mtk_ddp_comp_get_id(struct device_node *node,
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enum mtk_ddp_comp_type comp_type)
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{
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int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
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int i;
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for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
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if (comp_type == mtk_ddp_matches[i].type &&
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(id < 0 || id == mtk_ddp_matches[i].alias_id))
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return i;
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}
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return -EINVAL;
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}
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int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
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struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
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const struct mtk_ddp_comp_funcs *funcs)
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{
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enum mtk_ddp_comp_type type;
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struct device_node *larb_node;
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struct platform_device *larb_pdev;
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if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
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return -EINVAL;
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type = mtk_ddp_matches[comp_id].type;
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comp->id = comp_id;
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comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
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if (comp_id == DDP_COMPONENT_BLS ||
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comp_id == DDP_COMPONENT_DPI0 ||
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comp_id == DDP_COMPONENT_DPI1 ||
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comp_id == DDP_COMPONENT_DSI0 ||
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comp_id == DDP_COMPONENT_DSI1 ||
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comp_id == DDP_COMPONENT_DSI2 ||
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comp_id == DDP_COMPONENT_DSI3 ||
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comp_id == DDP_COMPONENT_PWM0) {
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comp->regs = NULL;
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comp->clk = NULL;
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comp->irq = 0;
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return 0;
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}
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comp->regs = of_iomap(node, 0);
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comp->irq = of_irq_get(node, 0);
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comp->clk = of_clk_get(node, 0);
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if (IS_ERR(comp->clk))
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return PTR_ERR(comp->clk);
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/* Only DMA capable components need the LARB property */
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comp->larb_dev = NULL;
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if (type != MTK_DISP_OVL &&
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type != MTK_DISP_RDMA &&
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type != MTK_DISP_WDMA)
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return 0;
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larb_node = of_parse_phandle(node, "mediatek,larb", 0);
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if (!larb_node) {
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dev_err(dev,
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"Missing mediadek,larb phandle in %pOF node\n", node);
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return -EINVAL;
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}
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larb_pdev = of_find_device_by_node(larb_node);
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if (!larb_pdev) {
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dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
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of_node_put(larb_node);
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return -EPROBE_DEFER;
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}
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of_node_put(larb_node);
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comp->larb_dev = &larb_pdev->dev;
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return 0;
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}
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int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
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{
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struct mtk_drm_private *private = drm->dev_private;
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if (private->ddp_comp[comp->id])
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return -EBUSY;
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private->ddp_comp[comp->id] = comp;
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return 0;
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}
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void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
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{
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struct mtk_drm_private *private = drm->dev_private;
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private->ddp_comp[comp->id] = NULL;
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}
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