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e96998fc20
According to the Armada 38x datasheet, the window base address
registers value is set in bits [31:4] of the register and corresponds
to the transaction address bits [47:20].
Therefore, the 32bit base address value should be shifted right by
20bits and left by 4bits, resulting in 16 bit shift right.
The bug as not been noticed yet because if the memory available on
the platform is less than 2GB, then the base address is zero.
[gregory.clement@free-electrons.com: add extra-explanation]
Fixes: a3464ed2f1 (ata: ahci_mvebu: new driver for Marvell Armada 380
AHCI interfaces)
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Tejun Heo <tj@kernel.org>
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* AHCI glue platform driver for Marvell EBU SOCs
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*
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* Copyright (C) 2014 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Marcin Wojtas <mw@semihalf.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/ahci_platform.h>
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#include <linux/kernel.h>
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#include <linux/mbus.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "ahci.h"
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#define DRV_NAME "ahci-mvebu"
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#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
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#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
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#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
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#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
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#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
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static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
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const struct mbus_dram_target_info *dram)
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{
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int i;
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for (i = 0; i < 4; i++) {
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writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
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writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
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writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel((cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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hpriv->mmio + AHCI_WINDOW_CTRL(i));
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writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
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writel(((cs->size - 1) & 0xffff0000),
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hpriv->mmio + AHCI_WINDOW_SIZE(i));
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}
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}
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static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
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{
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/*
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* Enable the regret bit to allow the SATA unit to regret a
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* request that didn't receive an acknowlegde and avoid a
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* deadlock
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*/
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writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
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writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
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}
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static const struct ata_port_info ahci_mvebu_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_platform_ops,
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};
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static struct scsi_host_template ahci_platform_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int ahci_mvebu_probe(struct platform_device *pdev)
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{
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struct ahci_host_priv *hpriv;
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const struct mbus_dram_target_info *dram;
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int rc;
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hpriv = ahci_platform_get_resources(pdev);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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dram = mv_mbus_dram_info();
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if (!dram)
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return -ENODEV;
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ahci_mvebu_mbus_config(hpriv, dram);
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ahci_mvebu_regret_option(hpriv);
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info,
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&ahci_platform_sht);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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static const struct of_device_id ahci_mvebu_of_match[] = {
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{ .compatible = "marvell,armada-380-ahci", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
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/*
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* We currently don't provide power management related operations,
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* since there is no suspend/resume support at the platform level for
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* Armada 38x for the moment.
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*/
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static struct platform_driver ahci_mvebu_driver = {
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.probe = ahci_mvebu_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ahci_mvebu_of_match,
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},
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};
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module_platform_driver(ahci_mvebu_driver);
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MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
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MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:ahci_mvebu");
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