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148f9bb877
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/x86 uses of the __cpuinit macros from
all C files. x86 only had the one __CPUINIT used in assembly files,
and it wasn't paired off with a .previous or a __FINIT, so we can
delete it directly w/o any corresponding additional change there.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Acked-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
501 lines
11 KiB
C
501 lines
11 KiB
C
#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/processor.h>
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#include <asm/e820.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "cpu.h"
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#ifdef CONFIG_X86_OOSTORE
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static u32 power2(u32 x)
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{
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u32 s = 1;
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while (s <= x)
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s <<= 1;
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return s >>= 1;
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}
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/*
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* Set up an actual MCR
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*/
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static void centaur_mcr_insert(int reg, u32 base, u32 size, int key)
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{
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u32 lo, hi;
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hi = base & ~0xFFF;
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lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
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lo &= ~0xFFF; /* Remove the ctrl value bits */
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lo |= key; /* Attribute we wish to set */
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wrmsr(reg+MSR_IDT_MCR0, lo, hi);
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mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
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}
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/*
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* Figure what we can cover with MCR's
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*
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* Shortcut: We know you can't put 4Gig of RAM on a winchip
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*/
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static u32 ramtop(void)
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{
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u32 clip = 0xFFFFFFFFUL;
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u32 top = 0;
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int i;
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for (i = 0; i < e820.nr_map; i++) {
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unsigned long start, end;
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if (e820.map[i].addr > 0xFFFFFFFFUL)
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continue;
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/*
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* Don't MCR over reserved space. Ignore the ISA hole
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* we frob around that catastrophe already
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*/
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if (e820.map[i].type == E820_RESERVED) {
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if (e820.map[i].addr >= 0x100000UL &&
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e820.map[i].addr < clip)
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clip = e820.map[i].addr;
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continue;
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}
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start = e820.map[i].addr;
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end = e820.map[i].addr + e820.map[i].size;
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if (start >= end)
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continue;
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if (end > top)
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top = end;
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}
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/*
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* Everything below 'top' should be RAM except for the ISA hole.
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* Because of the limited MCR's we want to map NV/ACPI into our
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* MCR range for gunk in RAM
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*
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* Clip might cause us to MCR insufficient RAM but that is an
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* acceptable failure mode and should only bite obscure boxes with
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* a VESA hole at 15Mb
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*
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* The second case Clip sometimes kicks in is when the EBDA is marked
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* as reserved. Again we fail safe with reasonable results
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*/
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if (top > clip)
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top = clip;
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return top;
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}
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/*
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* Compute a set of MCR's to give maximum coverage
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*/
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static int centaur_mcr_compute(int nr, int key)
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{
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u32 mem = ramtop();
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u32 root = power2(mem);
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u32 base = root;
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u32 top = root;
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u32 floor = 0;
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int ct = 0;
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while (ct < nr) {
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u32 fspace = 0;
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u32 high;
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u32 low;
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/*
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* Find the largest block we will fill going upwards
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*/
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high = power2(mem-top);
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/*
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* Find the largest block we will fill going downwards
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*/
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low = base/2;
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/*
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* Don't fill below 1Mb going downwards as there
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* is an ISA hole in the way.
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*/
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if (base <= 1024*1024)
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low = 0;
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/*
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* See how much space we could cover by filling below
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* the ISA hole
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*/
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if (floor == 0)
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fspace = 512*1024;
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else if (floor == 512*1024)
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fspace = 128*1024;
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/* And forget ROM space */
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/*
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* Now install the largest coverage we get
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*/
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if (fspace > high && fspace > low) {
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centaur_mcr_insert(ct, floor, fspace, key);
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floor += fspace;
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} else if (high > low) {
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centaur_mcr_insert(ct, top, high, key);
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top += high;
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} else if (low > 0) {
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base -= low;
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centaur_mcr_insert(ct, base, low, key);
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} else
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break;
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ct++;
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}
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/*
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* We loaded ct values. We now need to set the mask. The caller
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* must do this bit.
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*/
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return ct;
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}
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static void centaur_create_optimal_mcr(void)
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{
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int used;
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int i;
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/*
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* Allocate up to 6 mcrs to mark as much of ram as possible
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* as write combining and weak write ordered.
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*
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* To experiment with: Linux never uses stack operations for
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* mmio spaces so we could globally enable stack operation wc
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*
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* Load the registers with type 31 - full write combining, all
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* writes weakly ordered.
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*/
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used = centaur_mcr_compute(6, 31);
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/*
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* Wipe unused MCRs
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*/
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for (i = used; i < 8; i++)
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wrmsr(MSR_IDT_MCR0+i, 0, 0);
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}
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static void winchip2_create_optimal_mcr(void)
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{
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u32 lo, hi;
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int used;
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int i;
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/*
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* Allocate up to 6 mcrs to mark as much of ram as possible
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* as write combining, weak store ordered.
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*
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* Load the registers with type 25
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* 8 - weak write ordering
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* 16 - weak read ordering
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* 1 - write combining
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*/
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used = centaur_mcr_compute(6, 25);
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/*
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* Mark the registers we are using.
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*/
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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for (i = 0; i < used; i++)
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lo |= 1<<(9+i);
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/*
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* Wipe unused MCRs
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*/
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for (i = used; i < 8; i++)
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wrmsr(MSR_IDT_MCR0+i, 0, 0);
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}
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/*
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* Handle the MCR key on the Winchip 2.
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*/
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static void winchip2_unprotect_mcr(void)
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{
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u32 lo, hi;
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u32 key;
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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lo &= ~0x1C0; /* blank bits 8-6 */
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key = (lo>>17) & 7;
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lo |= key<<6; /* replace with unlock key */
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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}
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static void winchip2_protect_mcr(void)
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{
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u32 lo, hi;
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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lo &= ~0x1C0; /* blank bits 8-6 */
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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}
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#endif /* CONFIG_X86_OOSTORE */
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#define ACE_PRESENT (1 << 6)
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#define ACE_ENABLED (1 << 7)
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#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
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#define RNG_PRESENT (1 << 2)
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#define RNG_ENABLED (1 << 3)
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#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
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static void init_c3(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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/* Test for Centaur Extended Feature Flags presence */
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if (cpuid_eax(0xC0000000) >= 0xC0000001) {
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u32 tmp = cpuid_edx(0xC0000001);
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/* enable ACE unit, if present and disabled */
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if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
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rdmsr(MSR_VIA_FCR, lo, hi);
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lo |= ACE_FCR; /* enable ACE unit */
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wrmsr(MSR_VIA_FCR, lo, hi);
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printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
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}
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/* enable RNG unit, if present and disabled */
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if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
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rdmsr(MSR_VIA_RNG, lo, hi);
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lo |= RNG_ENABLE; /* enable RNG unit */
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wrmsr(MSR_VIA_RNG, lo, hi);
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printk(KERN_INFO "CPU: Enabled h/w RNG\n");
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}
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/* store Centaur Extended Feature Flags as
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* word 5 of the CPU capability bit array
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*/
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c->x86_capability[5] = cpuid_edx(0xC0000001);
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}
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#ifdef CONFIG_X86_32
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/* Cyrix III family needs CX8 & PGE explicitly enabled. */
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if (c->x86_model >= 6 && c->x86_model <= 13) {
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rdmsr(MSR_VIA_FCR, lo, hi);
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lo |= (1<<1 | 1<<7);
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wrmsr(MSR_VIA_FCR, lo, hi);
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set_cpu_cap(c, X86_FEATURE_CX8);
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}
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/* Before Nehemiah, the C3's had 3dNOW! */
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if (c->x86_model >= 6 && c->x86_model < 9)
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set_cpu_cap(c, X86_FEATURE_3DNOW);
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#endif
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if (c->x86 == 0x6 && c->x86_model >= 0xf) {
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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cpu_detect_cache_sizes(c);
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}
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enum {
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ECX8 = 1<<1,
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EIERRINT = 1<<2,
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DPM = 1<<3,
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DMCE = 1<<4,
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DSTPCLK = 1<<5,
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ELINEAR = 1<<6,
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DSMC = 1<<7,
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DTLOCK = 1<<8,
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EDCTLB = 1<<8,
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EMMX = 1<<9,
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DPDC = 1<<11,
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EBRPRED = 1<<12,
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DIC = 1<<13,
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DDC = 1<<14,
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DNA = 1<<15,
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ERETSTK = 1<<16,
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E2MMX = 1<<19,
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EAMD3D = 1<<20,
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};
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static void early_init_centaur(struct cpuinfo_x86 *c)
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{
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switch (c->x86) {
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#ifdef CONFIG_X86_32
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case 5:
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/* Emulate MTRRs using Centaur's MCR. */
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set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
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break;
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#endif
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case 6:
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if (c->x86_model >= 0xf)
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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break;
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}
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#endif
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}
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static void init_centaur(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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char *name;
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u32 fcr_set = 0;
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u32 fcr_clr = 0;
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u32 lo, hi, newlo;
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u32 aa, bb, cc, dd;
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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#endif
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early_init_centaur(c);
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switch (c->x86) {
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#ifdef CONFIG_X86_32
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case 5:
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switch (c->x86_model) {
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case 4:
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name = "C6";
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fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
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fcr_clr = DPDC;
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printk(KERN_NOTICE "Disabling bugged TSC.\n");
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clear_cpu_cap(c, X86_FEATURE_TSC);
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#ifdef CONFIG_X86_OOSTORE
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centaur_create_optimal_mcr();
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*
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* The C6 original lacks weak read order
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*
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* Note 0x120 is write only on Winchip 1
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*/
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wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
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#endif
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break;
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case 8:
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switch (c->x86_mask) {
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default:
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name = "2";
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break;
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case 7 ... 9:
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name = "2A";
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break;
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case 10 ... 15:
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name = "2B";
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break;
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}
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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#ifdef CONFIG_X86_OOSTORE
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winchip2_unprotect_mcr();
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winchip2_create_optimal_mcr();
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*/
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lo |= 31;
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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winchip2_protect_mcr();
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#endif
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break;
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case 9:
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name = "3";
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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#ifdef CONFIG_X86_OOSTORE
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winchip2_unprotect_mcr();
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winchip2_create_optimal_mcr();
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*/
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lo |= 31;
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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winchip2_protect_mcr();
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#endif
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break;
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default:
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name = "??";
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}
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rdmsr(MSR_IDT_FCR1, lo, hi);
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newlo = (lo|fcr_set) & (~fcr_clr);
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if (newlo != lo) {
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printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
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lo, newlo);
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wrmsr(MSR_IDT_FCR1, newlo, hi);
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} else {
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printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
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}
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/* Emulate MTRRs using Centaur's MCR. */
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set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
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/* Report CX8 */
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set_cpu_cap(c, X86_FEATURE_CX8);
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/* Set 3DNow! on Winchip 2 and above. */
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if (c->x86_model >= 8)
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set_cpu_cap(c, X86_FEATURE_3DNOW);
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/* See if we can find out some more. */
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if (cpuid_eax(0x80000000) >= 0x80000005) {
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/* Yes, we can. */
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cpuid(0x80000005, &aa, &bb, &cc, &dd);
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/* Add L1 data and code cache sizes. */
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c->x86_cache_size = (cc>>24)+(dd>>24);
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}
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sprintf(c->x86_model_id, "WinChip %s", name);
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break;
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#endif
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case 6:
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init_c3(c);
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break;
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}
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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#endif
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}
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static unsigned int
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centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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#ifdef CONFIG_X86_32
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/* VIA C3 CPUs (670-68F) need further shifting. */
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if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
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size >>= 8;
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/*
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* There's also an erratum in Nehemiah stepping 1, which
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* returns '65KB' instead of '64KB'
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* - Note, it seems this may only be in engineering samples.
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*/
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if ((c->x86 == 6) && (c->x86_model == 9) &&
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(c->x86_mask == 1) && (size == 65))
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size -= 1;
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#endif
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return size;
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}
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static const struct cpu_dev centaur_cpu_dev = {
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.c_vendor = "Centaur",
|
|
.c_ident = { "CentaurHauls" },
|
|
.c_early_init = early_init_centaur,
|
|
.c_init = init_centaur,
|
|
.c_size_cache = centaur_size_cache,
|
|
.c_x86_vendor = X86_VENDOR_CENTAUR,
|
|
};
|
|
|
|
cpu_dev_register(centaur_cpu_dev);
|