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76b4eda866
Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
115 lines
3.0 KiB
ArmAsm
115 lines
3.0 KiB
ArmAsm
/*
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* A2 specific assembly support code
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*
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* Copyright 2009 Ben Herrenschmidt, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/asm-offsets.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/processor.h>
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#include <asm/reg_a2.h>
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#include <asm/reg.h>
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#include <asm/thread_info.h>
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/*
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* Disable thdid and class fields in ERATs to bump PID to full 14 bits capacity.
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* This also prevents external LPID accesses but that isn't a problem when not a
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* guest. Under PV, this setting will be ignored and MMUCR will return the right
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* number of PID bits we can use.
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*/
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#define MMUCR1_EXTEND_PID \
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(MMUCR1_ICTID | MMUCR1_ITTID | MMUCR1_DCTID | \
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MMUCR1_DTTID | MMUCR1_DCCD)
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/*
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* Use extended PIDs if enabled.
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* Don't clear the ERATs on context sync events and enable I & D LRU.
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* Enable ERAT back invalidate when tlbwe overwrites an entry.
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*/
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#define INITIAL_MMUCR1 \
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(MMUCR1_EXTEND_PID | MMUCR1_CSINV_NEVER | MMUCR1_IRRE | \
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MMUCR1_DRRE | MMUCR1_TLBWE_BINV)
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_GLOBAL(__setup_cpu_a2)
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/* Some of these are actually thread local and some are
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* core local but doing it always won't hurt
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*/
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#ifdef CONFIG_PPC_WSP_COPRO
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/* Make sure ACOP starts out as zero */
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li r3,0
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mtspr SPRN_ACOP,r3
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/* Enable icswx instruction */
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mfspr r3,SPRN_A2_CCR2
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ori r3,r3,A2_CCR2_ENABLE_ICSWX
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mtspr SPRN_A2_CCR2,r3
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/* Unmask all CTs in HACOP */
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li r3,-1
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mtspr SPRN_HACOP,r3
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#endif /* CONFIG_PPC_WSP_COPRO */
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/* Enable doorbell */
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mfspr r3,SPRN_A2_CCR2
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oris r3,r3,A2_CCR2_ENABLE_PC@h
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mtspr SPRN_A2_CCR2,r3
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isync
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/* Setup CCR0 to disable power saving for now as it's busted
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* in the current implementations. Setup CCR1 to wake on
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* interrupts normally (we write the default value but who
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* knows what FW may have clobbered...)
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*/
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li r3,0
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mtspr SPRN_A2_CCR0, r3
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LOAD_REG_IMMEDIATE(r3,0x0f0f0f0f)
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mtspr SPRN_A2_CCR1, r3
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/* Initialise MMUCR1 */
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lis r3,INITIAL_MMUCR1@h
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ori r3,r3,INITIAL_MMUCR1@l
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mtspr SPRN_MMUCR1,r3
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/* Set MMUCR2 to enable 4K, 64K, 1M, 16M and 1G pages */
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LOAD_REG_IMMEDIATE(r3, 0x000a7531)
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mtspr SPRN_MMUCR2,r3
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/* Set MMUCR3 to write all thids bit to the TLB */
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LOAD_REG_IMMEDIATE(r3, 0x0000000f)
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mtspr SPRN_MMUCR3,r3
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/* Don't do ERAT stuff if running guest mode */
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mfmsr r3
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andis. r0,r3,MSR_GS@h
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bne 1f
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/* Now set the I-ERAT watermark to 15 */
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lis r4,(MMUCR0_TLBSEL_I|MMUCR0_ECL)@h
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mtspr SPRN_MMUCR0, r4
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li r4,A2_IERAT_SIZE-1
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PPC_ERATWE(r4,r4,3)
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/* Now set the D-ERAT watermark to 31 */
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lis r4,(MMUCR0_TLBSEL_D|MMUCR0_ECL)@h
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mtspr SPRN_MMUCR0, r4
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li r4,A2_DERAT_SIZE-1
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PPC_ERATWE(r4,r4,3)
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/* And invalidate the beast just in case. That won't get rid of
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* a bolted entry though it will be in LRU and so will go away eventually
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* but let's not bother for now
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*/
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PPC_ERATILX(0,0,0)
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1:
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blr
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_GLOBAL(__restore_cpu_a2)
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b __setup_cpu_a2
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