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9d0412680e
Now that Linux includes support for the Atmel AT91SAM9260 and AT91SAM9261 processors in addition to the original Atmel AT91RM9200 (with support for more AT91 processors pending), the "mach-at91rm9200" and "arch-at91rm9200" directories should be renamed to indicate their more generic nature. The following git commands should be run BEFORE applying this patch: git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91 git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91 Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
147 lines
6.7 KiB
C
147 lines
6.7 KiB
C
/*
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* include/asm-arm/arch-at91/at91_tc.h
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*
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* Copyright (C) SAN People
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*
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* Timer/Counter Unit (TC) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_TC_H
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#define AT91_TC_H
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#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
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#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
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#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
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#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
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#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
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#define AT91_TC_TC0XC0S_NONE (1 << 0)
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#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
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#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
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#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
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#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
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#define AT91_TC_TC1XC1S_NONE (1 << 2)
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#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
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#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
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#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
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#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
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#define AT91_TC_TC2XC2S_NONE (1 << 4)
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#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
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#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
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#define AT91_TC_CCR 0x00 /* Channel Control Register */
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#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
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#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
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#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
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#define AT91_TC_CMR 0x04 /* Channel Mode Register */
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#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
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#define AT91_TC_TIMER_CLOCK1 (0 << 0)
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#define AT91_TC_TIMER_CLOCK2 (1 << 0)
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#define AT91_TC_TIMER_CLOCK3 (2 << 0)
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#define AT91_TC_TIMER_CLOCK4 (3 << 0)
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#define AT91_TC_TIMER_CLOCK5 (4 << 0)
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#define AT91_TC_XC0 (5 << 0)
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#define AT91_TC_XC1 (6 << 0)
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#define AT91_TC_XC2 (7 << 0)
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#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
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#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
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#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
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#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
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#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
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#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
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#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
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#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
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#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
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#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
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#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
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#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
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#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
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#define AT91_TC_EEVTEDG_NONE (0 << 8)
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#define AT91_TC_EEVTEDG_RISING (1 << 8)
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#define AT91_TC_EEVTEDG_FALLING (2 << 8)
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#define AT91_TC_EEVTEDG_BOTH (3 << 8)
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#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
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#define AT91_TC_EEVT_TIOB (0 << 10)
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#define AT91_TC_EEVT_XC0 (1 << 10)
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#define AT91_TC_EEVT_XC1 (2 << 10)
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#define AT91_TC_EEVT_XC2 (3 << 10)
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#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
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#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
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#define AT91_TC_WAVESEL_UP (0 << 13)
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#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
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#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
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#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
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#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
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#define AT91_TC_ACPA_NONE (0 << 16)
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#define AT91_TC_ACPA_SET (1 << 16)
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#define AT91_TC_ACPA_CLEAR (2 << 16)
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#define AT91_TC_ACPA_TOGGLE (3 << 16)
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#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
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#define AT91_TC_ACPC_NONE (0 << 18)
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#define AT91_TC_ACPC_SET (1 << 18)
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#define AT91_TC_ACPC_CLEAR (2 << 18)
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#define AT91_TC_ACPC_TOGGLE (3 << 18)
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#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
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#define AT91_TC_AEEVT_NONE (0 << 20)
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#define AT91_TC_AEEVT_SET (1 << 20)
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#define AT91_TC_AEEVT_CLEAR (2 << 20)
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#define AT91_TC_AEEVT_TOGGLE (3 << 20)
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#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
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#define AT91_TC_ASWTRG_NONE (0 << 22)
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#define AT91_TC_ASWTRG_SET (1 << 22)
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#define AT91_TC_ASWTRG_CLEAR (2 << 22)
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#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
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#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
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#define AT91_TC_BCPB_NONE (0 << 24)
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#define AT91_TC_BCPB_SET (1 << 24)
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#define AT91_TC_BCPB_CLEAR (2 << 24)
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#define AT91_TC_BCPB_TOGGLE (3 << 24)
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#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
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#define AT91_TC_BCPC_NONE (0 << 26)
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#define AT91_TC_BCPC_SET (1 << 26)
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#define AT91_TC_BCPC_CLEAR (2 << 26)
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#define AT91_TC_BCPC_TOGGLE (3 << 26)
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#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
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#define AT91_TC_BEEVT_NONE (0 << 28)
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#define AT91_TC_BEEVT_SET (1 << 28)
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#define AT91_TC_BEEVT_CLEAR (2 << 28)
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#define AT91_TC_BEEVT_TOGGLE (3 << 28)
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#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
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#define AT91_TC_BSWTRG_NONE (0 << 30)
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#define AT91_TC_BSWTRG_SET (1 << 30)
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#define AT91_TC_BSWTRG_CLEAR (2 << 30)
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#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
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#define AT91_TC_CV 0x10 /* Counter Value */
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#define AT91_TC_RA 0x14 /* Register A */
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#define AT91_TC_RB 0x18 /* Register B */
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#define AT91_TC_RC 0x1c /* Register C */
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#define AT91_TC_SR 0x20 /* Status Register */
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#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
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#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
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#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
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#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
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#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
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#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
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#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
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#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
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#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
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#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
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#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
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#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
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#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
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#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
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#endif
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