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a312b37b2a
Call paravirt_pagetable_setup_{start,done}
These paravirt_ops functions were not being called on x86_64.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Cc: Stephen Tweedie <sct@redhat.com>
Cc: Mark McLoughlin <markmc@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
190 lines
5.5 KiB
C
190 lines
5.5 KiB
C
#ifndef _I386_PGTABLE_H
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#define _I386_PGTABLE_H
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* the i386, we use that, but "fold" the mid level into the top-level page
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* table, so that we physically have the same two-level page table as the
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* i386 mmu expects.
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*
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* This file contains the functions and defines necessary to modify and use
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* the i386 page table tree.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <linux/threads.h>
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#include <asm/paravirt.h>
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#include <linux/bitops.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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struct mm_struct;
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struct vm_area_struct;
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extern pgd_t swapper_pg_dir[1024];
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static inline void pgtable_cache_init(void) { }
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static inline void check_pgt_cache(void) { }
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void paging_init(void);
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/*
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* The Linux x86 paging architecture is 'compile-time dual-mode', it
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* implements both the traditional 2-level x86 page tables and the
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* newer 3-level PAE-mode page tables.
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*/
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level-defs.h>
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# define PMD_SIZE (1UL << PMD_SHIFT)
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# define PMD_MASK (~(PMD_SIZE - 1))
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#else
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# include <asm/pgtable-2level-defs.h>
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#endif
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE - 1))
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/* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 8MB value just means that there will be a 8MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*/
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#define VMALLOC_OFFSET (8 * 1024 * 1024)
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#define VMALLOC_START (((unsigned long)high_memory + 2 * VMALLOC_OFFSET - 1) \
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& ~(VMALLOC_OFFSET - 1))
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#ifdef CONFIG_X86_PAE
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#define LAST_PKMAP 512
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#else
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#define LAST_PKMAP 1024
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#endif
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#define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE * (LAST_PKMAP + 1)) \
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& PMD_MASK)
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#ifdef CONFIG_HIGHMEM
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# define VMALLOC_END (PKMAP_BASE - 2 * PAGE_SIZE)
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#else
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# define VMALLOC_END (FIXADDR_START - 2 * PAGE_SIZE)
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#endif
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/*
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* Define this if things work differently on an i386 and an i486:
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* it will (on an i486) warn about kernel memory accesses that are
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* done without a 'access_ok(VERIFY_WRITE,..)'
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*/
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#undef TEST_ACCESS_OK
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/* The boot page tables (all created as a single array) */
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extern unsigned long pg0[];
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#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
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/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
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#define pmd_none(x) (!(unsigned long)pmd_val((x)))
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#define pmd_present(x) (pmd_val((x)) & _PAGE_PRESENT)
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#define pmd_bad(x) ((pmd_val(x) & (~PTE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
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#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level.h>
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#else
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# include <asm/pgtable-2level.h>
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#endif
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/*
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* Macro to mark a page protection value as "uncacheable".
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* On processors which do not support it, this is a no-op.
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*/
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#define pgprot_noncached(prot) \
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((boot_cpu_data.x86 > 3) \
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? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) \
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: (prot))
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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static inline int pud_large(pud_t pud) { return 0; }
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/*
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* the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
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*
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* this macro returns the index of the entry in the pmd page which would
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* control the given virtual address
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*/
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#define pmd_index(address) \
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(((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
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/*
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* the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
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*
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* this macro returns the index of the entry in the pte page which would
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* control the given virtual address
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*/
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#define pte_index(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) \
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((pte_t *)pmd_page_vaddr(*(dir)) + pte_index((address)))
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#define pmd_page(pmd) (pfn_to_page(pmd_val((pmd)) >> PAGE_SHIFT))
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#define pmd_page_vaddr(pmd) \
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((unsigned long)__va(pmd_val((pmd)) & PTE_MASK))
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#if defined(CONFIG_HIGHPTE)
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#define pte_offset_map(dir, address) \
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((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE0) + \
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pte_index((address)))
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#define pte_offset_map_nested(dir, address) \
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((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE1) + \
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pte_index((address)))
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#define pte_unmap(pte) kunmap_atomic((pte), KM_PTE0)
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#define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1)
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#else
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
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#define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address))
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#endif
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/* Clear a kernel PTE and flush it from the TLB */
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#define kpte_clear_flush(ptep, vaddr) \
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do { \
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pte_clear(&init_mm, (vaddr), (ptep)); \
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__flush_tlb_one((vaddr)); \
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} while (0)
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/*
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* The i386 doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information.
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*/
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#define update_mmu_cache(vma, address, pte) do { } while (0)
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#endif /* !__ASSEMBLY__ */
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/*
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* kern_addr_valid() is (1) for FLATMEM and (0) for
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* SPARSEMEM and DISCONTIGMEM
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*/
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#ifdef CONFIG_FLATMEM
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#define kern_addr_valid(addr) (1)
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#else
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#define kern_addr_valid(kaddr) (0)
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#endif
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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#endif /* _I386_PGTABLE_H */
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