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bc05ea63b3
BlueField-3 uses the same control registers in tmfifo access but at different addresses. This commit replaces the offset reference with pointers, and set up these pointers in the probe functions accordingly. Signed-off-by: Liming Sun <limings@nvidia.com> Reviewed-by: David Thompson <davthompson@nvidia.com> Reviewed-by: Vadim Pasternak <vadimp@nvidia.com> Link: https://lore.kernel.org/r/20221018133303.243920-1-limings@nvidia.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
74 lines
3.0 KiB
C
74 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019, Mellanox Technologies. All rights reserved.
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*/
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#ifndef __MLXBF_TMFIFO_REGS_H__
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#define __MLXBF_TMFIFO_REGS_H__
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#include <linux/types.h>
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#include <linux/bits.h>
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#define MLXBF_TMFIFO_TX_DATA 0x00
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#define MLXBF_TMFIFO_TX_STS 0x08
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#define MLXBF_TMFIFO_TX_STS__LENGTH 0x0001
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#define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 0
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#define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 9
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#define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 0
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#define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_TX_CTL 0x10
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#define MLXBF_TMFIFO_TX_CTL__LENGTH 0x0001
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#define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 0
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#define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 8
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#define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 128
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#define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 8
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#define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 8
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#define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 128
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#define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 32
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 9
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 256
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
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#define MLXBF_TMFIFO_RX_DATA 0x00
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#define MLXBF_TMFIFO_RX_STS 0x08
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#define MLXBF_TMFIFO_RX_STS__LENGTH 0x0001
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#define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 0
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#define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 9
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#define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 0
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#define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_RX_CTL 0x10
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#define MLXBF_TMFIFO_RX_CTL__LENGTH 0x0001
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#define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 0
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#define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 8
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#define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 128
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#define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 8
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#define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 8
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#define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 128
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#define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
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#define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8)
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 32
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 9
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 256
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0)
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#define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32)
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/* BF3 register offsets within resource 0. */
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#define MLXBF_TMFIFO_RX_DATA_BF3 0x0000
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#define MLXBF_TMFIFO_TX_DATA_BF3 0x1000
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/* BF3 register offsets within resource 1. */
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#define MLXBF_TMFIFO_RX_STS_BF3 0x0000
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#define MLXBF_TMFIFO_RX_CTL_BF3 0x0008
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#define MLXBF_TMFIFO_TX_STS_BF3 0x0100
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#define MLXBF_TMFIFO_TX_CTL_BF3 0x0108
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#endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */
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