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The same file in libdrm is, as is the tradition with the rest of libdrm, etc, using an MIT license. To avoid complications in the future with sync'ing the uapi header to libdrm, lets fix the license mismatch now before there are any non-trivial commits from someone other than myself. Cc: Emil Velikov <emil.l.velikov@gmail.com> Cc: Gabriel Laskar <gabriel@lse.epita.fr> Cc: Mikko Rapeli <mikko.rapeli@iki.fi> Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
279 lines
11 KiB
C
279 lines
11 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MSM_DRM_H__
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#define __MSM_DRM_H__
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints:
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* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
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* user/kernel compatibility
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* 2) Keep fields aligned to their size
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* 3) Because of how drm_ioctl() works, we can add new fields at
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* the end of an ioctl if some care is taken: drm_ioctl() will
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* zero out the new fields at the tail of the ioctl, so a zero
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* value should have a backwards compatible meaning. And for
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* output params, userspace won't see the newly added output
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* fields.. so that has to be somehow ok.
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*/
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#define MSM_PIPE_NONE 0x00
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#define MSM_PIPE_2D0 0x01
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_3D0 0x10
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/* The pipe-id just uses the lower bits, so can be OR'd with flags in
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* the upper 16 bits (which could be extended further, if needed, maybe
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* we extend/overload the pipe-id some day to deal with multiple rings,
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* but even then I don't think we need the full lower 16 bits).
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*/
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#define MSM_PIPE_ID_MASK 0xffff
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#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
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#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
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/* timeouts are specified in clock-monotonic absolute times (to simplify
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* restarting interrupted ioctls). The following struct is logically the
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* same as 'struct timespec' but 32/64b ABI safe.
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*/
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struct drm_msm_timespec {
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__s64 tv_sec; /* seconds */
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__s64 tv_nsec; /* nanoseconds */
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};
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#define MSM_PARAM_GPU_ID 0x01
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#define MSM_PARAM_GMEM_SIZE 0x02
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#define MSM_PARAM_CHIP_ID 0x03
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#define MSM_PARAM_MAX_FREQ 0x04
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#define MSM_PARAM_TIMESTAMP 0x05
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struct drm_msm_param {
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__u32 pipe; /* in, MSM_PIPE_x */
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__u32 param; /* in, MSM_PARAM_x */
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__u64 value; /* out (get_param) or in (set_param) */
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};
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/*
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* GEM buffers:
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*/
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#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
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#define MSM_BO_GPU_READONLY 0x00000002
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#define MSM_BO_CACHE_MASK 0x000f0000
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/* cache modes */
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#define MSM_BO_CACHED 0x00010000
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#define MSM_BO_WC 0x00020000
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#define MSM_BO_UNCACHED 0x00040000
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#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
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MSM_BO_GPU_READONLY | \
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MSM_BO_CACHED | \
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MSM_BO_WC | \
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MSM_BO_UNCACHED)
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struct drm_msm_gem_new {
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__u64 size; /* in */
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__u32 flags; /* in, mask of MSM_BO_x */
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__u32 handle; /* out */
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};
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struct drm_msm_gem_info {
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__u32 handle; /* in */
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__u32 pad;
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__u64 offset; /* out, offset to pass to mmap() */
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};
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#define MSM_PREP_READ 0x01
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#define MSM_PREP_WRITE 0x02
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#define MSM_PREP_NOSYNC 0x04
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#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
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struct drm_msm_gem_cpu_prep {
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__u32 handle; /* in */
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__u32 op; /* in, mask of MSM_PREP_x */
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struct drm_msm_timespec timeout; /* in */
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};
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struct drm_msm_gem_cpu_fini {
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__u32 handle; /* in */
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};
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/*
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* Cmdstream Submission:
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*/
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/* The value written into the cmdstream is logically:
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*
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* ((relocbuf->gpuaddr + reloc_offset) << shift) | or
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*
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* When we have GPU's w/ >32bit ptrs, it should be possible to deal
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* with this by emit'ing two reloc entries with appropriate shift
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* values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
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*
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* NOTE that reloc's must be sorted by order of increasing submit_offset,
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* otherwise EINVAL.
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*/
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struct drm_msm_gem_submit_reloc {
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__u32 submit_offset; /* in, offset from submit_bo */
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__u32 or; /* in, value OR'd with result */
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__s32 shift; /* in, amount of left shift (can be negative) */
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__u32 reloc_idx; /* in, index of reloc_bo buffer */
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__u64 reloc_offset; /* in, offset from start of reloc_bo */
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};
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/* submit-types:
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* BUF - this cmd buffer is executed normally.
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* IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
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* processed normally, but the kernel does not setup an IB to
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* this buffer in the first-level ringbuffer
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* CTX_RESTORE_BUF - only executed if there has been a GPU context
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* switch since the last SUBMIT ioctl
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*/
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#define MSM_SUBMIT_CMD_BUF 0x0001
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#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
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#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
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struct drm_msm_gem_submit_cmd {
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__u32 type; /* in, one of MSM_SUBMIT_CMD_x */
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__u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
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__u32 submit_offset; /* in, offset into submit_bo */
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__u32 size; /* in, cmdstream size */
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__u32 pad;
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__u32 nr_relocs; /* in, number of submit_reloc's */
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__u64 __user relocs; /* in, ptr to array of submit_reloc's */
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};
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/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
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* cmdstream buffer(s) themselves or reloc entries) has one (and only
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* one) entry in the submit->bos[] table.
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*
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* As a optimization, the current buffer (gpu virtual address) can be
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* passed back through the 'presumed' field. If on a subsequent reloc,
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* userspace passes back a 'presumed' address that is still valid,
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* then patching the cmdstream for this entry is skipped. This can
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* avoid kernel needing to map/access the cmdstream bo in the common
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* case.
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*/
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#define MSM_SUBMIT_BO_READ 0x0001
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#define MSM_SUBMIT_BO_WRITE 0x0002
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#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
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struct drm_msm_gem_submit_bo {
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__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
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__u32 handle; /* in, GEM handle */
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__u64 presumed; /* in/out, presumed buffer address */
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};
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/* Valid submit ioctl flags: */
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#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
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#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
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#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
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#define MSM_SUBMIT_FLAGS ( \
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MSM_SUBMIT_NO_IMPLICIT | \
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MSM_SUBMIT_FENCE_FD_IN | \
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MSM_SUBMIT_FENCE_FD_OUT | \
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0)
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/* Each cmdstream submit consists of a table of buffers involved, and
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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*/
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struct drm_msm_gem_submit {
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__u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
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__u32 fence; /* out */
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__u32 nr_bos; /* in, number of submit_bo's */
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__u32 nr_cmds; /* in, number of submit_cmd's */
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__u64 __user bos; /* in, ptr to array of submit_bo's */
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__u64 __user cmds; /* in, ptr to array of submit_cmd's */
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__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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* a buffer if you need to access it from the CPU (other cmdstream
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* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
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* handle the required synchronization under the hood). This ioctl
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* mainly just exists as a way to implement the gallium pipe_fence
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* APIs without requiring a dummy bo to synchronize on.
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*/
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struct drm_msm_wait_fence {
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__u32 fence; /* in */
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__u32 pad;
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struct drm_msm_timespec timeout; /* in */
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};
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/* madvise provides a way to tell the kernel in case a buffers contents
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* can be discarded under memory pressure, which is useful for userspace
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* bo cache where we want to optimistically hold on to buffer allocate
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* and potential mmap, but allow the pages to be discarded under memory
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* pressure.
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*
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* Typical usage would involve madvise(DONTNEED) when buffer enters BO
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* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
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* In the WILLNEED case, 'retained' indicates to userspace whether the
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* backing pages still exist.
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*/
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#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
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#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
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#define __MSM_MADV_PURGED 2 /* internal state */
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struct drm_msm_gem_madvise {
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__u32 handle; /* in, GEM handle */
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__u32 madv; /* in, MSM_MADV_x */
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__u32 retained; /* out, whether backing store still exists */
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};
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#define DRM_MSM_GET_PARAM 0x00
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/* placeholder:
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#define DRM_MSM_SET_PARAM 0x01
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*/
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#define DRM_MSM_GEM_NEW 0x02
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#define DRM_MSM_GEM_INFO 0x03
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#define DRM_MSM_GEM_CPU_PREP 0x04
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#define DRM_MSM_GEM_CPU_FINI 0x05
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#define DRM_MSM_GEM_SUBMIT 0x06
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#define DRM_MSM_WAIT_FENCE 0x07
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#define DRM_MSM_GEM_MADVISE 0x08
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#define DRM_MSM_NUM_IOCTLS 0x09
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#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
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#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
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#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
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#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
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#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __MSM_DRM_H__ */
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