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d3fa72e455
Pass struct dev pointer to dma_cache_sync() dma_cache_sync() is ill-designed in that it does not have a struct device pointer argument which makes proper support for systems that consist of a mix of coherent and non-coherent DMA devices hard. Change dma_cache_sync to take a struct device pointer as first argument and fix all its callers to pass it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: James Bottomley <James.Bottomley@steeleye.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
170 lines
4.4 KiB
C
170 lines
4.4 KiB
C
#ifndef __ASM_SH_DMA_MAPPING_H
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#define __ASM_SH_DMA_MAPPING_H
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#include <linux/mm.h>
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#include <asm/scatterlist.h>
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#include <asm/io.h>
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struct pci_dev;
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extern void *consistent_alloc(struct pci_dev *hwdev, size_t size,
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dma_addr_t *dma_handle);
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extern void consistent_free(struct pci_dev *hwdev, size_t size,
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void *vaddr, dma_addr_t dma_handle);
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#define dma_supported(dev, mask) (1)
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static inline int dma_set_mask(struct device *dev, u64 mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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return consistent_alloc(NULL, size, dma_handle);
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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consistent_free(NULL, size, vaddr, dma_handle);
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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dma_cache_wback_inv((unsigned long)vaddr, size);
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}
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static inline dma_addr_t dma_map_single(struct device *dev,
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void *ptr, size_t size,
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enum dma_data_direction dir)
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{
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#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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if (dev->bus == &pci_bus_type)
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return virt_to_bus(ptr);
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#endif
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dma_cache_sync(ptr, size, dir);
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return virt_to_bus(ptr);
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}
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#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
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static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir)
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{
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int i;
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for (i = 0; i < nents; i++) {
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#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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dma_cache_sync(page_address(sg[i].page) + sg[i].offset,
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sg[i].length, dir);
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#endif
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sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
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}
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return nents;
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}
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#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
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static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir)
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{
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return dma_map_single(dev, page_address(page) + offset, size, dir);
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}
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static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size, enum dma_data_direction dir)
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{
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dma_unmap_single(dev, dma_address, size, dir);
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}
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static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir)
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{
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#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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if (dev->bus == &pci_bus_type)
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return;
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#endif
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dma_cache_sync(bus_to_virt(dma_handle), size, dir);
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}
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static inline void dma_sync_single_range(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction dir)
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{
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#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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if (dev->bus == &pci_bus_type)
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return;
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#endif
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dma_cache_sync(bus_to_virt(dma_handle) + offset, size, dir);
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}
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static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir)
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{
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int i;
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for (i = 0; i < nelems; i++) {
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#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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dma_cache_sync(page_address(sg[i].page) + sg[i].offset,
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sg[i].length, dir);
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#endif
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sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
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}
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}
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static inline void dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single(dev, dma_handle, size, dir);
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}
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static inline void dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single(dev, dma_handle, size, dir);
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}
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static inline void dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction dir)
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{
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dma_sync_sg(dev, sg, nelems, dir);
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}
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static inline void dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction dir)
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{
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dma_sync_sg(dev, sg, nelems, dir);
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}
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static inline int dma_get_cache_alignment(void)
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{
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/*
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* Each processor family will define its own L1_CACHE_SHIFT,
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* L1_CACHE_BYTES wraps to this, so this is always safe.
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*/
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return L1_CACHE_BYTES;
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}
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static inline int dma_mapping_error(dma_addr_t dma_addr)
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{
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return dma_addr == 0;
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}
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#endif /* __ASM_SH_DMA_MAPPING_H */
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