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Add device tree bindings for video clock controller for SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-4-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
35 lines
901 B
C
35 lines
901 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_MVS0_CLK_SRC 0
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#define VIDEO_CC_MVS0C_CLK 1
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#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 2
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#define VIDEO_CC_MVS1_CLK_SRC 3
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#define VIDEO_CC_MVS1_DIV2_CLK 4
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#define VIDEO_CC_MVS1C_CLK 5
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#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 6
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#define VIDEO_CC_PLL0 7
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#define VIDEO_CC_PLL1 8
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/* VIDEO_CC resets */
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#define VIDEO_CC_CVP_INTERFACE_BCR 0
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#define VIDEO_CC_CVP_MVS0_BCR 1
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#define VIDEO_CC_MVS0C_CLK_ARES 2
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#define VIDEO_CC_CVP_MVS0C_BCR 3
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#define VIDEO_CC_CVP_MVS1_BCR 4
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#define VIDEO_CC_MVS1C_CLK_ARES 5
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#define VIDEO_CC_CVP_MVS1C_BCR 6
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#define MVS0C_GDSC 0
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#define MVS1C_GDSC 1
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#define MVS0_GDSC 2
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#define MVS1_GDSC 3
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#endif
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