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The OMAP watchdog timer driver needs to determine what caused the SoC to reset for its GETBOOTSTATUS ioctl. So, define a set of standard reset sources across OMAP SoCs. For OMAP2xxx, 3xxx, and 4xxx SoCs, define mappings from the SoC-specific reset source register bits to the standardized reset source IDs. Create SoC-specific PRM functions that read the appropriate per-SoC register and use the mapping to return the standardized reset bits. Register the SoC-specific PRM functions with the common PRM code via prm_register(). Create a function in the common PRM code, prm_read_reset_sources(), that calls the SoC-specific function, registered during boot. This patch does not yet handle some SoCs, such as AM33xx. Those SoCs were not handled by the code this will replace. Signed-off-by: Paul Walmsley <paul@pwsan.com>
110 lines
3.1 KiB
C
110 lines
3.1 KiB
C
/*
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* OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
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*
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
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#define __ARCH_ARM_MACH_OMAP2_PRM_H
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#include "prcm-common.h"
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/*
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* 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
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*
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* 2430: PM_PWSTST_MDM
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*
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* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
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* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
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* PM_PWSTST_NEON
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*/
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#define OMAP_INTRANSITION_MASK (1 << 20)
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/*
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* 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
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*
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* 2430: PM_PWSTST_MDM
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*
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* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
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* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
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* PM_PWSTST_NEON
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*/
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#define OMAP_POWERSTATEST_SHIFT 0
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#define OMAP_POWERSTATEST_MASK (0x3 << 0)
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/*
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* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSP, PM_PWSTST_MPU
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*
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* 2430: PM_PWSTCTRL_MDM shared bits
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*
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* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
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* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
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* PM_PWSTCTRL_NEON shared bits
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*/
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#define OMAP_POWERSTATE_SHIFT 0
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#define OMAP_POWERSTATE_MASK (0x3 << 0)
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/*
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* Standardized OMAP reset source bits
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*
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* To the extent these happen to match the hardware register bit
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* shifts, it's purely coincidental. Used by omap-wdt.c.
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* OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
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* there are any bits remaining in the global PRM_RSTST register that
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* haven't been identified, or when the PRM code for the current SoC
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* doesn't know how to interpret the register.
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*/
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#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0
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#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1
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#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2
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#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
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#define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4
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#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5
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#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6
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#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7
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#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8
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#define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9
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#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10
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#define OMAP_C2C_RST_SRC_ID_SHIFT 11
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#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12
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#ifndef __ASSEMBLER__
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/**
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* struct prm_reset_src_map - map register bitshifts to standard bitshifts
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* @reg_shift: bitshift in the PRM reset source register
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* @std_shift: bitshift equivalent in the standard reset source list
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*
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* The fields are signed because -1 is used as a terminator.
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*/
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struct prm_reset_src_map {
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s8 reg_shift;
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s8 std_shift;
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};
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/**
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* struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
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* @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl
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*/
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struct prm_ll_data {
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u32 (*read_reset_sources)(void);
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};
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extern int prm_register(struct prm_ll_data *pld);
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extern int prm_unregister(struct prm_ll_data *pld);
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extern u32 prm_read_reset_sources(void);
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#endif
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#endif
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