mirror of
https://github.com/torvalds/linux.git
synced 2024-11-15 08:31:55 +00:00
29de76240e
Partial Reconfiguration (PR) is the most important function for FME. It allows reconfiguration for given Port/Accelerated Function Unit (AFU). It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges, and invokes fpga-region's interface (fpga_region_program_fpga) for PR operation once PR request received via ioctl. Below user space interface is exposed by this sub feature. Ioctl interface: * DFL_FPGA_FME_PORT_PR Do partial reconfiguration per information from userspace, including target port(AFU), buffer size and address info. It returns error code to userspace if failed. For detailed PR error information, user needs to read fpga-mgr's status sysfs interface. Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> Signed-off-by: Shiva Rao <shiva.rao@intel.com> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> Signed-off-by: Kang Luwei <luwei.kang@intel.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
40 lines
1.4 KiB
Makefile
40 lines
1.4 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
#
|
|
# Makefile for the fpga framework and fpga manager drivers.
|
|
#
|
|
|
|
# Core FPGA Manager Framework
|
|
obj-$(CONFIG_FPGA) += fpga-mgr.o
|
|
|
|
# FPGA Manager Drivers
|
|
obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
|
|
obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
|
|
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
|
|
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
|
|
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
|
|
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
|
|
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
|
|
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
|
|
|
|
# FPGA Bridge Drivers
|
|
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
|
|
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
|
|
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
|
|
obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
|
|
|
|
# High Level Interfaces
|
|
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
|
|
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
|
|
|
|
# FPGA Device Feature List Support
|
|
obj-$(CONFIG_FPGA_DFL) += dfl.o
|
|
obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
|
|
|
|
dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
|
|
|
|
# Drivers for FPGAs which implement DFL
|
|
obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
|