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29a002776b
This patch fixes up ia64 kexec support for HP rx2620 hardware. It does this by skipping migration of already disabled irqs. This is most likely a problem on other ia64 platforms as well, but I've only been able to reproduce it on one machine so far. The full story is that handle_bad_irq() gets invoked before starting the new kernel without this patch. This seems to happen when fixup_irqs() calls generic_handle_irq() on already migrated (and disabled) irqs. So by avoiding migration of disabled irqs we stay away of handle_bad_irq(). The code has been tested on three different ia64 machines, all with good results. It is possible to trigger the same bug by offlining a processor using echo 0 > /sys/devices/system/cpu/cpuX/online. More detailed information is available in the following mail thread: http://lists.osdl.org/pipermail/fastboot/2007-January/thread.html#5774 Signed-off-by: Magnus Damm <magnus@valinux.co.jp> Acked-by: Simon Horman <horms@verge.net.au> Acked-by: Zou, Nanhai <nanhai.zou@intel.com> Acked-by: Jay Lan <jlan@sgi.com> Acked-by: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
218 lines
5.1 KiB
C
218 lines
5.1 KiB
C
/*
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* linux/arch/ia64/kernel/irq.c
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*
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* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
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*
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* This file contains the code used by various IRQ handling routines:
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* asking for different IRQ's should be done through these routines
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* instead of just grabbing them. Thus setups with different IRQ numbers
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* shouldn't result in any weird surprises, and installing new handlers
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* should be easier.
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*
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* Copyright (C) Ashok Raj<ashok.raj@intel.com>, Intel Corporation 2004
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*
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* 4/14/2004: Added code to handle cpu migration and do safe irq
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* migration without lossing interrupts for iosapic
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* architecture.
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*/
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#include <asm/delay.h>
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#include <asm/uaccess.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", irq, smp_processor_id());
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}
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#ifdef CONFIG_IA64_GENERIC
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unsigned int __ia64_local_vector_to_irq (ia64_vector vec)
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{
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return (unsigned int) vec;
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}
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#endif
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/*
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* Interrupt statistics:
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*/
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atomic_t irq_err_count;
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/*
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* /proc/interrupts printing:
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j;
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struct irqaction * action;
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unsigned long flags;
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j) {
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seq_printf(p, "CPU%d ",j);
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}
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ",i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j) {
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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}
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#endif
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seq_printf(p, " %14s", irq_desc[i].chip->name);
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seq_printf(p, " %s", action->name);
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for (action=action->next; action; action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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} else if (i == NR_IRQS)
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seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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return 0;
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}
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#ifdef CONFIG_SMP
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static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
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void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
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{
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cpumask_t mask = CPU_MASK_NONE;
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cpu_set(cpu_logical_id(hwid), mask);
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if (irq < NR_IRQS) {
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irq_desc[irq].affinity = mask;
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irq_redir[irq] = (char) (redir & 0xff);
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}
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_HOTPLUG_CPU
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unsigned int vectors_in_migration[NR_IRQS];
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/*
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* Since cpu_online_map is already updated, we just need to check for
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* affinity that has zeros
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*/
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static void migrate_irqs(void)
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{
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cpumask_t mask;
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irq_desc_t *desc;
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int irq, new_cpu;
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for (irq=0; irq < NR_IRQS; irq++) {
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desc = irq_desc + irq;
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if (desc->status == IRQ_DISABLED)
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continue;
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/*
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* No handling for now.
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* TBD: Implement a disable function so we can now
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* tell CPU not to respond to these local intr sources.
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* such as ITV,CPEI,MCA etc.
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*/
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if (desc->status == IRQ_PER_CPU)
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continue;
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cpus_and(mask, irq_desc[irq].affinity, cpu_online_map);
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if (any_online_cpu(mask) == NR_CPUS) {
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/*
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* Save it for phase 2 processing
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*/
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vectors_in_migration[irq] = irq;
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new_cpu = any_online_cpu(cpu_online_map);
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mask = cpumask_of_cpu(new_cpu);
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/*
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* Al three are essential, currently WARN_ON.. maybe panic?
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*/
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if (desc->chip && desc->chip->disable &&
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desc->chip->enable && desc->chip->set_affinity) {
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desc->chip->disable(irq);
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desc->chip->set_affinity(irq, mask);
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desc->chip->enable(irq);
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} else {
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WARN_ON((!(desc->chip) || !(desc->chip->disable) ||
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!(desc->chip->enable) ||
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!(desc->chip->set_affinity)));
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}
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}
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}
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}
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void fixup_irqs(void)
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{
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unsigned int irq;
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extern void ia64_process_pending_intr(void);
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extern void ia64_disable_timer(void);
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extern volatile int time_keeper_id;
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ia64_disable_timer();
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/*
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* Find a new timesync master
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*/
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if (smp_processor_id() == time_keeper_id) {
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time_keeper_id = first_cpu(cpu_online_map);
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printk ("CPU %d is now promoted to time-keeper master\n", time_keeper_id);
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}
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/*
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* Phase 1: Locate irq's bound to this cpu and
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* relocate them for cpu removal.
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*/
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migrate_irqs();
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/*
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* Phase 2: Perform interrupt processing for all entries reported in
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* local APIC.
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*/
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ia64_process_pending_intr();
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/*
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* Phase 3: Now handle any interrupts not captured in local APIC.
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* This is to account for cases that device interrupted during the time the
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* rte was being disabled and re-programmed.
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*/
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for (irq=0; irq < NR_IRQS; irq++) {
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if (vectors_in_migration[irq]) {
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struct pt_regs *old_regs = set_irq_regs(NULL);
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vectors_in_migration[irq]=0;
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generic_handle_irq(irq);
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set_irq_regs(old_regs);
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}
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}
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/*
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* Now let processor die. We do irq disable and max_xtp() to
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* ensure there is no more interrupts routed to this processor.
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* But the local timer interrupt can have 1 pending which we
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* take care in timer_interrupt().
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*/
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max_xtp();
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local_irq_disable();
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}
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#endif
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