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If vcpu has a interrupt in vmx non-root mode, injecting that interrupt requires a vmexit. With posted interrupt processing, the vmexit is not needed, and interrupts are fully taken care of by hardware. In nested vmx, this feature avoids much more vmexits than non-nested vmx. When L1 asks L0 to deliver L1's posted interrupt vector, and the target VCPU is in non-root mode, we use a physical ipi to deliver POSTED_INTR_NV to the target vCPU. Using POSTED_INTR_NV avoids unexpected interrupts if a concurrent vmexit happens and L1's vector is different with L0's. The IPI triggers posted interrupt processing in the target physical CPU. In case the target vCPU was not in guest mode, complete the posted interrupt delivery on the next entry to L2. Signed-off-by: Wincy Van <fanwenyi0529@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
176 lines
5.1 KiB
C
176 lines
5.1 KiB
C
#ifndef __KVM_X86_LAPIC_H
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#define __KVM_X86_LAPIC_H
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#include "iodev.h"
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#include <linux/kvm_host.h>
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#define KVM_APIC_INIT 0
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#define KVM_APIC_SIPI 1
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struct kvm_timer {
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struct hrtimer timer;
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s64 period; /* unit: ns */
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u32 timer_mode;
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u32 timer_mode_mask;
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u64 tscdeadline;
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u64 expired_tscdeadline;
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atomic_t pending; /* accumulated triggered timers */
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};
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struct kvm_lapic {
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unsigned long base_address;
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struct kvm_io_device dev;
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struct kvm_timer lapic_timer;
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u32 divide_count;
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struct kvm_vcpu *vcpu;
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bool sw_enabled;
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bool irr_pending;
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/* Number of bits set in ISR. */
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s16 isr_count;
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/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
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int highest_isr_cache;
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/**
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* APIC register page. The layout matches the register layout seen by
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* the guest 1:1, because it is accessed by the vmx microcode.
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* Note: Only one register, the TPR, is used by the microcode.
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*/
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void *regs;
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gpa_t vapic_addr;
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struct gfn_to_hva_cache vapic_cache;
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unsigned long pending_events;
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unsigned int sipi_vector;
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};
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int kvm_create_lapic(struct kvm_vcpu *vcpu);
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void kvm_free_lapic(struct kvm_vcpu *vcpu);
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int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
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int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
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int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
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void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
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void kvm_lapic_reset(struct kvm_vcpu *vcpu);
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u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
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void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
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void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
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void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
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u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
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void kvm_apic_set_version(struct kvm_vcpu *vcpu);
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void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr);
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void __kvm_apic_update_irr(u32 *pir, void *regs);
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void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
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unsigned long *dest_map);
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int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
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bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map);
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u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
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int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
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struct kvm_lapic_state *s);
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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
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u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
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void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
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void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
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void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
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int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
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void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
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void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
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int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
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}
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int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
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void kvm_lapic_init(void);
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static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
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{
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return *((u32 *) (apic->regs + reg_off));
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}
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extern struct static_key kvm_no_apic_vcpu;
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static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu)
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{
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if (static_key_false(&kvm_no_apic_vcpu))
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return vcpu->arch.apic;
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return true;
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}
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extern struct static_key_deferred apic_hw_disabled;
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static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
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{
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if (static_key_false(&apic_hw_disabled.key))
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return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
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return MSR_IA32_APICBASE_ENABLE;
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}
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extern struct static_key_deferred apic_sw_disabled;
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static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
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{
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if (static_key_false(&apic_sw_disabled.key))
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return apic->sw_enabled;
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return true;
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}
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static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
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}
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static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
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{
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return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
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}
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static inline int apic_x2apic_mode(struct kvm_lapic *apic)
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{
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return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
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}
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static inline bool kvm_apic_vid_enabled(struct kvm *kvm)
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{
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return kvm_x86_ops->vm_has_apicv(kvm);
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}
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static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
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{
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u16 cid;
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ldr >>= 32 - map->ldr_bits;
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cid = (ldr >> map->cid_shift) & map->cid_mask;
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return cid;
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}
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static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
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{
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ldr >>= (32 - map->ldr_bits);
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return ldr & map->lid_mask;
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}
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static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.apic->pending_events;
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}
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bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
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void wait_lapic_expire(struct kvm_vcpu *vcpu);
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#endif
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