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0b56e9a7e8
Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
262 lines
7.6 KiB
C
262 lines
7.6 KiB
C
/*
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* ST SPEAr1310-miphy driver
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*
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* Copyright (C) 2014 ST Microelectronics
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* Pratyush Anand <pratyush.anand@gmail.com>
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* Mohit Kumar <mohit.kumar.dhaka@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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/* SPEAr1310 Registers */
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#define SPEAR1310_PCIE_SATA_CFG 0x3A4
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#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
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#define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
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#define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
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#define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
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#define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
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#define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
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#define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
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#define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
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#define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
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#define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
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#define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
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#define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
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#define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
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#define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
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#define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
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#define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
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#define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
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#define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
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#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
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#define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
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#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
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#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
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#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
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#define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
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#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
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#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
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#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
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#define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
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#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
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#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
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#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
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#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
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BIT((x + 29)))
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#define SPEAR1310_PCIE_CFG_VAL(x) \
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(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
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SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
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SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
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SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
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SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
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#define SPEAR1310_SATA_CFG_VAL(x) \
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(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
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SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
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SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
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SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
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SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
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#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
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#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
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#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
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#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
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#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
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#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
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#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
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(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
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SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
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SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
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SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
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(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
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(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
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SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
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#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
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enum spear1310_miphy_mode {
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SATA,
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PCIE,
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};
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struct spear1310_miphy_priv {
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/* instance id of this phy */
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u32 id;
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/* phy mode: 0 for SATA 1 for PCIe */
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enum spear1310_miphy_mode mode;
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/* regmap for any soc specific misc registers */
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struct regmap *misc;
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/* phy struct pointer */
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struct phy *phy;
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};
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static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
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{
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u32 val;
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
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SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
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SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
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switch (priv->id) {
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case 0:
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val = SPEAR1310_PCIE_CFG_VAL(0);
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break;
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case 1:
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val = SPEAR1310_PCIE_CFG_VAL(1);
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break;
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case 2:
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val = SPEAR1310_PCIE_CFG_VAL(2);
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
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SPEAR1310_PCIE_CFG_MASK(priv->id), val);
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return 0;
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}
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static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
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{
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
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SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
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SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
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return 0;
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}
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static int spear1310_miphy_init(struct phy *phy)
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{
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struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
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int ret = 0;
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if (priv->mode == PCIE)
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ret = spear1310_miphy_pcie_init(priv);
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return ret;
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}
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static int spear1310_miphy_exit(struct phy *phy)
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{
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struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
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int ret = 0;
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if (priv->mode == PCIE)
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ret = spear1310_miphy_pcie_exit(priv);
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return ret;
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}
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static const struct of_device_id spear1310_miphy_of_match[] = {
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{ .compatible = "st,spear1310-miphy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
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static const struct phy_ops spear1310_miphy_ops = {
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.init = spear1310_miphy_init,
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.exit = spear1310_miphy_exit,
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.owner = THIS_MODULE,
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};
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static struct phy *spear1310_miphy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
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if (args->args_count < 1) {
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dev_err(dev, "DT did not pass correct no of args\n");
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return ERR_PTR(-ENODEV);
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}
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priv->mode = args->args[0];
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if (priv->mode != SATA && priv->mode != PCIE) {
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dev_err(dev, "DT did not pass correct phy mode\n");
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return ERR_PTR(-ENODEV);
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}
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return priv->phy;
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}
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static int spear1310_miphy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spear1310_miphy_priv *priv;
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struct phy_provider *phy_provider;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->misc =
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syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
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if (IS_ERR(priv->misc)) {
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dev_err(dev, "failed to find misc regmap\n");
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return PTR_ERR(priv->misc);
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}
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if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
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dev_err(dev, "failed to find phy id\n");
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return -EINVAL;
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}
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priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create SATA PCIe PHY\n");
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return PTR_ERR(priv->phy);
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}
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dev_set_drvdata(dev, priv);
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phy_set_drvdata(priv->phy, priv);
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phy_provider =
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devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
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if (IS_ERR(phy_provider)) {
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dev_err(dev, "failed to register phy provider\n");
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return PTR_ERR(phy_provider);
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}
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return 0;
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}
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static struct platform_driver spear1310_miphy_driver = {
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.probe = spear1310_miphy_probe,
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.driver = {
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.name = "spear1310-miphy",
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.of_match_table = of_match_ptr(spear1310_miphy_of_match),
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},
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};
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module_platform_driver(spear1310_miphy_driver);
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MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
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MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
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MODULE_LICENSE("GPL v2");
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