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6a1197457f
In ksz9021_load_values_from_of() val2 to val4 aren't tested against their initialization value. This causes the test to always succeed, and this value to be used as if it was loaded from the devicetree instead of being ignored, in case of a missing/invalid property in the ethernet OF device node. As a result, the value "0" is written to the relevant registers. Change the conditions to test against the right initialization value. Signed-off-by: Hubert Chaumette <hchaumette@adeneo-embedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
542 lines
15 KiB
C
542 lines
15 KiB
C
/*
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* drivers/net/phy/micrel.c
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*
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* Driver for Micrel PHYs
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*
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* Author: David J. Choi
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*
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* Copyright (c) 2010-2013 Micrel, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Support : Micrel Phys:
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* Giga phys: ksz9021, ksz9031
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* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
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* ksz8021, ksz8031, ksz8051,
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* ksz8081, ksz8091,
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* ksz8061,
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* Switch : ksz8873, ksz886x
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/micrel_phy.h>
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#include <linux/of.h>
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/* Operation Mode Strap Override */
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#define MII_KSZPHY_OMSO 0x16
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#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
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#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
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#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
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/* general Interrupt control/status reg in vendor specific block. */
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#define MII_KSZPHY_INTCS 0x1B
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#define KSZPHY_INTCS_JABBER (1 << 15)
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#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
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#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
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#define KSZPHY_INTCS_PARELLEL (1 << 12)
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#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
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#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
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#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
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#define KSZPHY_INTCS_LINK_UP (1 << 8)
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#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
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KSZPHY_INTCS_LINK_DOWN)
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/* general PHY control reg in vendor specific block. */
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#define MII_KSZPHY_CTRL 0x1F
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/* bitmap of PHY register to set interrupt mode */
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#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
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#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
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/* Write/read to/from extended registers */
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#define MII_KSZPHY_EXTREG 0x0b
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#define KSZPHY_EXTREG_WRITE 0x8000
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#define MII_KSZPHY_EXTREG_WRITE 0x0c
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#define MII_KSZPHY_EXTREG_READ 0x0d
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/* Extended registers */
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#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
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#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
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#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
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#define PS_TO_REG 200
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static int ksz_config_flags(struct phy_device *phydev)
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{
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int regval;
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if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
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regval = phy_read(phydev, MII_KSZPHY_CTRL);
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regval |= KSZ8051_RMII_50MHZ_CLK;
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return phy_write(phydev, MII_KSZPHY_CTRL, regval);
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}
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return 0;
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}
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static int kszphy_extended_write(struct phy_device *phydev,
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u32 regnum, u16 val)
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{
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phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
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return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
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}
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static int kszphy_extended_read(struct phy_device *phydev,
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u32 regnum)
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{
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phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
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return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
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}
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static int kszphy_ack_interrupt(struct phy_device *phydev)
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{
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/* bit[7..0] int status, which is a read and clear register. */
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int rc;
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rc = phy_read(phydev, MII_KSZPHY_INTCS);
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return (rc < 0) ? rc : 0;
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}
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static int kszphy_set_interrupt(struct phy_device *phydev)
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{
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int temp;
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temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
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KSZPHY_INTCS_ALL : 0;
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return phy_write(phydev, MII_KSZPHY_INTCS, temp);
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}
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static int kszphy_config_intr(struct phy_device *phydev)
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{
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int temp, rc;
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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rc = kszphy_set_interrupt(phydev);
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return rc < 0 ? rc : 0;
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}
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static int ksz9021_config_intr(struct phy_device *phydev)
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{
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int temp, rc;
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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rc = kszphy_set_interrupt(phydev);
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return rc < 0 ? rc : 0;
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}
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static int ks8737_config_intr(struct phy_device *phydev)
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{
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int temp, rc;
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/* set the interrupt pin active low */
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temp = phy_read(phydev, MII_KSZPHY_CTRL);
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temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
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phy_write(phydev, MII_KSZPHY_CTRL, temp);
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rc = kszphy_set_interrupt(phydev);
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return rc < 0 ? rc : 0;
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}
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static int kszphy_setup_led(struct phy_device *phydev,
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unsigned int reg, unsigned int shift)
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{
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struct device *dev = &phydev->dev;
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struct device_node *of_node = dev->of_node;
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int rc, temp;
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u32 val;
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if (!of_node && dev->parent->of_node)
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of_node = dev->parent->of_node;
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if (of_property_read_u32(of_node, "micrel,led-mode", &val))
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return 0;
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temp = phy_read(phydev, reg);
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if (temp < 0)
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return temp;
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temp &= ~(3 << shift);
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temp |= val << shift;
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rc = phy_write(phydev, reg, temp);
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return rc < 0 ? rc : 0;
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}
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static int kszphy_config_init(struct phy_device *phydev)
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{
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return 0;
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}
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static int kszphy_config_init_led8041(struct phy_device *phydev)
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{
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/* single led control, register 0x1e bits 15..14 */
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return kszphy_setup_led(phydev, 0x1e, 14);
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}
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static int ksz8021_config_init(struct phy_device *phydev)
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{
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const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
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int rc;
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rc = kszphy_setup_led(phydev, 0x1f, 4);
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if (rc)
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dev_err(&phydev->dev, "failed to set led mode\n");
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phy_write(phydev, MII_KSZPHY_OMSO, val);
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rc = ksz_config_flags(phydev);
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return rc < 0 ? rc : 0;
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}
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static int ks8051_config_init(struct phy_device *phydev)
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{
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int rc;
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rc = kszphy_setup_led(phydev, 0x1f, 4);
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if (rc)
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dev_err(&phydev->dev, "failed to set led mode\n");
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rc = ksz_config_flags(phydev);
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return rc < 0 ? rc : 0;
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}
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static int ksz9021_load_values_from_of(struct phy_device *phydev,
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struct device_node *of_node, u16 reg,
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char *field1, char *field2,
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char *field3, char *field4)
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{
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int val1 = -1;
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int val2 = -2;
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int val3 = -3;
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int val4 = -4;
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int newval;
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int matches = 0;
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if (!of_property_read_u32(of_node, field1, &val1))
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matches++;
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if (!of_property_read_u32(of_node, field2, &val2))
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matches++;
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if (!of_property_read_u32(of_node, field3, &val3))
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matches++;
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if (!of_property_read_u32(of_node, field4, &val4))
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matches++;
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if (!matches)
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return 0;
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if (matches < 4)
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newval = kszphy_extended_read(phydev, reg);
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else
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newval = 0;
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if (val1 != -1)
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newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
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if (val2 != -2)
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newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
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if (val3 != -3)
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newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
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if (val4 != -4)
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newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
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return kszphy_extended_write(phydev, reg, newval);
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}
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static int ksz9021_config_init(struct phy_device *phydev)
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{
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struct device *dev = &phydev->dev;
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struct device_node *of_node = dev->of_node;
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if (!of_node && dev->parent->of_node)
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of_node = dev->parent->of_node;
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if (of_node) {
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
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"txen-skew-ps", "txc-skew-ps",
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"rxdv-skew-ps", "rxc-skew-ps");
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_RX_DATA_PAD_SKEW,
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"rxd0-skew-ps", "rxd1-skew-ps",
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"rxd2-skew-ps", "rxd3-skew-ps");
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_TX_DATA_PAD_SKEW,
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"txd0-skew-ps", "txd1-skew-ps",
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"txd2-skew-ps", "txd3-skew-ps");
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}
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return 0;
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}
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#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
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#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
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#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
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static int ksz8873mll_read_status(struct phy_device *phydev)
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{
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int regval;
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/* dummy read */
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regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
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regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
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if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
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phydev->duplex = DUPLEX_HALF;
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else
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phydev->duplex = DUPLEX_FULL;
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if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
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phydev->speed = SPEED_10;
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else
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phydev->speed = SPEED_100;
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phydev->link = 1;
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phydev->pause = phydev->asym_pause = 0;
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return 0;
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}
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static int ksz8873mll_config_aneg(struct phy_device *phydev)
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{
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return 0;
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}
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static struct phy_driver ksphy_driver[] = {
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{
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.phy_id = PHY_ID_KS8737,
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.phy_id_mask = 0x00fffff0,
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.name = "Micrel KS8737",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = ks8737_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8021,
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.phy_id_mask = 0x00ffffff,
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.name = "Micrel KSZ8021 or KSZ8031",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
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SUPPORTED_Asym_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = ksz8021_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8031,
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.phy_id_mask = 0x00ffffff,
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.name = "Micrel KSZ8031",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
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SUPPORTED_Asym_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = ksz8021_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8041,
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.phy_id_mask = 0x00fffff0,
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.name = "Micrel KSZ8041",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
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| SUPPORTED_Asym_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init_led8041,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8041RNLI,
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.phy_id_mask = 0x00fffff0,
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.name = "Micrel KSZ8041RNLI",
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.features = PHY_BASIC_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init_led8041,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8051,
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.phy_id_mask = 0x00fffff0,
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.name = "Micrel KSZ8051",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
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| SUPPORTED_Asym_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = ks8051_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8001,
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.name = "Micrel KSZ8001 or KS8721",
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.phy_id_mask = 0x00ffffff,
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init_led8041,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8081,
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.name = "Micrel KSZ8081 or KSZ8091",
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.phy_id_mask = 0x00fffff0,
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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.config_intr = kszphy_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = { .owner = THIS_MODULE,},
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}, {
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.phy_id = PHY_ID_KSZ8061,
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.name = "Micrel KSZ8061",
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.phy_id_mask = 0x00fffff0,
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = kszphy_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.driver = { .owner = THIS_MODULE,},
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ9021,
|
|
.phy_id_mask = 0x000ffffe,
|
|
.name = "Micrel KSZ9021 Gigabit PHY",
|
|
.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = ksz9021_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = ksz9021_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.driver = { .owner = THIS_MODULE, },
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ9031,
|
|
.phy_id_mask = 0x00fffff0,
|
|
.name = "Micrel KSZ9031 Gigabit PHY",
|
|
.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
|
|
| SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.ack_interrupt = kszphy_ack_interrupt,
|
|
.config_intr = ksz9021_config_intr,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.driver = { .owner = THIS_MODULE, },
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ8873MLL,
|
|
.phy_id_mask = 0x00fffff0,
|
|
.name = "Micrel KSZ8873MLL Switch",
|
|
.features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
|
|
.flags = PHY_HAS_MAGICANEG,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = ksz8873mll_config_aneg,
|
|
.read_status = ksz8873mll_read_status,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.driver = { .owner = THIS_MODULE, },
|
|
}, {
|
|
.phy_id = PHY_ID_KSZ886X,
|
|
.phy_id_mask = 0x00fffff0,
|
|
.name = "Micrel KSZ886X Switch",
|
|
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
|
|
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
|
|
.config_init = kszphy_config_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = genphy_read_status,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.driver = { .owner = THIS_MODULE, },
|
|
} };
|
|
|
|
static int __init ksphy_init(void)
|
|
{
|
|
return phy_drivers_register(ksphy_driver,
|
|
ARRAY_SIZE(ksphy_driver));
|
|
}
|
|
|
|
static void __exit ksphy_exit(void)
|
|
{
|
|
phy_drivers_unregister(ksphy_driver,
|
|
ARRAY_SIZE(ksphy_driver));
|
|
}
|
|
|
|
module_init(ksphy_init);
|
|
module_exit(ksphy_exit);
|
|
|
|
MODULE_DESCRIPTION("Micrel PHY driver");
|
|
MODULE_AUTHOR("David J. Choi");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
static struct mdio_device_id __maybe_unused micrel_tbl[] = {
|
|
{ PHY_ID_KSZ9021, 0x000ffffe },
|
|
{ PHY_ID_KSZ9031, 0x00fffff0 },
|
|
{ PHY_ID_KSZ8001, 0x00ffffff },
|
|
{ PHY_ID_KS8737, 0x00fffff0 },
|
|
{ PHY_ID_KSZ8021, 0x00ffffff },
|
|
{ PHY_ID_KSZ8031, 0x00ffffff },
|
|
{ PHY_ID_KSZ8041, 0x00fffff0 },
|
|
{ PHY_ID_KSZ8051, 0x00fffff0 },
|
|
{ PHY_ID_KSZ8061, 0x00fffff0 },
|
|
{ PHY_ID_KSZ8081, 0x00fffff0 },
|
|
{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
|
|
{ PHY_ID_KSZ886X, 0x00fffff0 },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, micrel_tbl);
|