mirror of
https://github.com/torvalds/linux.git
synced 2024-11-18 10:01:43 +00:00
90e9311a34
Convert the whole of locore.S (assembly to enter guest and handle exception entry) to be generated dynamically with uasm. This is done with minimal changes to the resulting code. The main changes are: - Some constants are generated by uasm using LUI+ADDIU instead of LUI+ORI. - Loading of lo and hi are swapped around in vcpu_run but not when resuming the guest after an exit. Both bits of logic are now generated by the same code. - Register MOVEs in uasm use different ADDU operand ordering to GNU as, putting zero register into rs instead of rt. - The JALR.HB to call the C exit handler is switched to JALR, since the hazard barrier would appear to be unnecessary. This will allow further optimisation in the future to dynamically handle the capabilities of the CPU. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim KrÄmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
51 lines
1.8 KiB
C
51 lines
1.8 KiB
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* KVM/MIPS: Interrupts
|
|
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
|
* Authors: Sanjay Lal <sanjayl@kymasys.com>
|
|
*/
|
|
|
|
/*
|
|
* MIPS Exception Priorities, exceptions (including interrupts) are queued up
|
|
* for the guest in the order specified by their priorities
|
|
*/
|
|
|
|
#define MIPS_EXC_RESET 0
|
|
#define MIPS_EXC_SRESET 1
|
|
#define MIPS_EXC_DEBUG_ST 2
|
|
#define MIPS_EXC_DEBUG 3
|
|
#define MIPS_EXC_DDB 4
|
|
#define MIPS_EXC_NMI 5
|
|
#define MIPS_EXC_MCHK 6
|
|
#define MIPS_EXC_INT_TIMER 7
|
|
#define MIPS_EXC_INT_IO 8
|
|
#define MIPS_EXC_EXECUTE 9
|
|
#define MIPS_EXC_INT_IPI_1 10
|
|
#define MIPS_EXC_INT_IPI_2 11
|
|
#define MIPS_EXC_MAX 12
|
|
/* XXXSL More to follow */
|
|
|
|
#define C_TI (_ULCAST_(1) << 30)
|
|
|
|
#define KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE (0)
|
|
#define KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE (0)
|
|
|
|
void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority);
|
|
void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority);
|
|
int kvm_mips_pending_timer(struct kvm_vcpu *vcpu);
|
|
|
|
void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu);
|
|
void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu);
|
|
void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
|
|
struct kvm_mips_interrupt *irq);
|
|
void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
|
|
struct kvm_mips_interrupt *irq);
|
|
int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
|
u32 cause);
|
|
int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
|
|
u32 cause);
|
|
void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause);
|