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f7018c2135
The drivers/video directory is a mess. It contains generic video related files, directories for backlight, console, linux logo, lots of fbdev device drivers, fbdev framework files. Make some order into the chaos by creating drivers/video/fbdev directory, and move all fbdev related files there. No functionality is changed, although I guess it is possible that some subtle Makefile build order related issue could be created by this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Clark <robdclark@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
333 lines
7.6 KiB
C
333 lines
7.6 KiB
C
/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __SHARE_H__
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#define __SHARE_H__
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#include "via_modesetting.h"
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/* Define Bit Field */
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#define BIT0 0x01
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#define BIT1 0x02
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#define BIT2 0x04
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#define BIT3 0x08
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#define BIT4 0x10
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#define BIT5 0x20
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#define BIT6 0x40
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#define BIT7 0x80
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/* Video Memory Size */
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#define VIDEO_MEMORY_SIZE_16M 0x1000000
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/*
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* Lengths of the VPIT structure arrays.
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*/
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#define StdCR 0x19
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#define StdSR 0x04
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#define StdGR 0x09
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#define StdAR 0x14
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#define PatchCR 11
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/* Display path */
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#define IGA1 1
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#define IGA2 2
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/* Define Color Depth */
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#define MODE_8BPP 1
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#define MODE_16BPP 2
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#define MODE_32BPP 4
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#define GR20 0x20
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#define GR21 0x21
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#define GR22 0x22
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/* Sequencer Registers */
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#define SR01 0x01
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#define SR10 0x10
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#define SR12 0x12
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#define SR15 0x15
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#define SR16 0x16
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#define SR17 0x17
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#define SR18 0x18
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#define SR1B 0x1B
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#define SR1A 0x1A
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#define SR1C 0x1C
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#define SR1D 0x1D
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#define SR1E 0x1E
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#define SR1F 0x1F
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#define SR20 0x20
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#define SR21 0x21
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#define SR22 0x22
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#define SR2A 0x2A
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#define SR2D 0x2D
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#define SR2E 0x2E
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#define SR30 0x30
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#define SR39 0x39
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#define SR3D 0x3D
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#define SR3E 0x3E
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#define SR3F 0x3F
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#define SR40 0x40
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#define SR43 0x43
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#define SR44 0x44
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#define SR45 0x45
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#define SR46 0x46
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#define SR47 0x47
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#define SR48 0x48
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#define SR49 0x49
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#define SR4A 0x4A
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#define SR4B 0x4B
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#define SR4C 0x4C
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#define SR52 0x52
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#define SR57 0x57
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#define SR58 0x58
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#define SR59 0x59
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#define SR5D 0x5D
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#define SR5E 0x5E
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#define SR65 0x65
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/* CRT Controller Registers */
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#define CR00 0x00
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#define CR01 0x01
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#define CR02 0x02
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#define CR03 0x03
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#define CR04 0x04
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#define CR05 0x05
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#define CR06 0x06
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#define CR07 0x07
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#define CR08 0x08
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#define CR09 0x09
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#define CR0A 0x0A
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#define CR0B 0x0B
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#define CR0C 0x0C
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#define CR0D 0x0D
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#define CR0E 0x0E
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#define CR0F 0x0F
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#define CR10 0x10
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#define CR11 0x11
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#define CR12 0x12
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#define CR13 0x13
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#define CR14 0x14
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#define CR15 0x15
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#define CR16 0x16
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#define CR17 0x17
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#define CR18 0x18
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/* Extend CRT Controller Registers */
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#define CR30 0x30
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#define CR31 0x31
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#define CR32 0x32
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#define CR33 0x33
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#define CR34 0x34
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#define CR35 0x35
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#define CR36 0x36
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#define CR37 0x37
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#define CR38 0x38
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#define CR39 0x39
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#define CR3A 0x3A
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#define CR3B 0x3B
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#define CR3C 0x3C
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#define CR3D 0x3D
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#define CR3E 0x3E
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#define CR3F 0x3F
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#define CR40 0x40
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#define CR41 0x41
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#define CR42 0x42
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#define CR43 0x43
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#define CR44 0x44
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#define CR45 0x45
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#define CR46 0x46
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#define CR47 0x47
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#define CR48 0x48
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#define CR49 0x49
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#define CR4A 0x4A
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#define CR4B 0x4B
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#define CR4C 0x4C
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#define CR4D 0x4D
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#define CR4E 0x4E
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#define CR4F 0x4F
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#define CR50 0x50
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#define CR51 0x51
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#define CR52 0x52
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#define CR53 0x53
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#define CR54 0x54
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#define CR55 0x55
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#define CR56 0x56
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#define CR57 0x57
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#define CR58 0x58
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#define CR59 0x59
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#define CR5A 0x5A
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#define CR5B 0x5B
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#define CR5C 0x5C
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#define CR5D 0x5D
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#define CR5E 0x5E
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#define CR5F 0x5F
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#define CR60 0x60
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#define CR61 0x61
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#define CR62 0x62
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#define CR63 0x63
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#define CR64 0x64
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#define CR65 0x65
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#define CR66 0x66
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#define CR67 0x67
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#define CR68 0x68
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#define CR69 0x69
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#define CR6A 0x6A
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#define CR6B 0x6B
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#define CR6C 0x6C
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#define CR6D 0x6D
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#define CR6E 0x6E
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#define CR6F 0x6F
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#define CR70 0x70
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#define CR71 0x71
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#define CR72 0x72
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#define CR73 0x73
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#define CR74 0x74
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#define CR75 0x75
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#define CR76 0x76
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#define CR77 0x77
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#define CR78 0x78
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#define CR79 0x79
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#define CR7A 0x7A
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#define CR7B 0x7B
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#define CR7C 0x7C
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#define CR7D 0x7D
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#define CR7E 0x7E
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#define CR7F 0x7F
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#define CR80 0x80
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#define CR81 0x81
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#define CR82 0x82
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#define CR83 0x83
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#define CR84 0x84
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#define CR85 0x85
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#define CR86 0x86
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#define CR87 0x87
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#define CR88 0x88
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#define CR89 0x89
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#define CR8A 0x8A
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#define CR8B 0x8B
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#define CR8C 0x8C
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#define CR8D 0x8D
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#define CR8E 0x8E
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#define CR8F 0x8F
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#define CR90 0x90
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#define CR91 0x91
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#define CR92 0x92
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#define CR93 0x93
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#define CR94 0x94
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#define CR95 0x95
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#define CR96 0x96
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#define CR97 0x97
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#define CR98 0x98
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#define CR99 0x99
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#define CR9A 0x9A
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#define CR9B 0x9B
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#define CR9C 0x9C
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#define CR9D 0x9D
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#define CR9E 0x9E
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#define CR9F 0x9F
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#define CRA0 0xA0
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#define CRA1 0xA1
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#define CRA2 0xA2
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#define CRA3 0xA3
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#define CRD2 0xD2
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#define CRD3 0xD3
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#define CRD4 0xD4
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/* LUT Table*/
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#define LUT_DATA 0x3C9 /* DACDATA */
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#define LUT_INDEX_READ 0x3C7 /* DACRX */
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#define LUT_INDEX_WRITE 0x3C8 /* DACWX */
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#define DACMASK 0x3C6
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/* Definition Device */
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#define DEVICE_CRT 0x01
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#define DEVICE_DVI 0x03
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#define DEVICE_LCD 0x04
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/* Device output interface */
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#define INTERFACE_NONE 0x00
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#define INTERFACE_ANALOG_RGB 0x01
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#define INTERFACE_DVP0 0x02
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#define INTERFACE_DVP1 0x03
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#define INTERFACE_DFP_HIGH 0x04
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#define INTERFACE_DFP_LOW 0x05
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#define INTERFACE_DFP 0x06
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#define INTERFACE_LVDS0 0x07
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#define INTERFACE_LVDS1 0x08
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#define INTERFACE_LVDS0LVDS1 0x09
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#define INTERFACE_TMDS 0x0A
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#define HW_LAYOUT_LCD_ONLY 0x01
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#define HW_LAYOUT_DVI_ONLY 0x02
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#define HW_LAYOUT_LCD_DVI 0x03
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#define HW_LAYOUT_LCD1_LCD2 0x04
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#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
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/* Definition CRTC Timing Index */
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#define H_TOTAL_INDEX 0
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#define H_ADDR_INDEX 1
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#define H_BLANK_START_INDEX 2
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#define H_BLANK_END_INDEX 3
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#define H_SYNC_START_INDEX 4
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#define H_SYNC_END_INDEX 5
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#define V_TOTAL_INDEX 6
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#define V_ADDR_INDEX 7
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#define V_BLANK_START_INDEX 8
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#define V_BLANK_END_INDEX 9
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#define V_SYNC_START_INDEX 10
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#define V_SYNC_END_INDEX 11
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#define H_TOTAL_SHADOW_INDEX 12
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#define H_BLANK_END_SHADOW_INDEX 13
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#define V_TOTAL_SHADOW_INDEX 14
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#define V_ADDR_SHADOW_INDEX 15
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#define V_BLANK_SATRT_SHADOW_INDEX 16
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#define V_BLANK_END_SHADOW_INDEX 17
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#define V_SYNC_SATRT_SHADOW_INDEX 18
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#define V_SYNC_END_SHADOW_INDEX 19
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/* LCD display method
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*/
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#define LCD_EXPANDSION 0x00
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#define LCD_CENTERING 0x01
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/* LCD mode
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*/
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#define LCD_OPENLDI 0x00
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#define LCD_SPWG 0x01
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struct crt_mode_table {
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int refresh_rate;
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int h_sync_polarity;
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int v_sync_polarity;
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struct via_display_timing crtc;
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};
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struct io_reg {
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int port;
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u8 index;
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u8 mask;
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u8 value;
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};
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#endif /* __SHARE_H__ */
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