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Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
138 lines
3.6 KiB
C
138 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H
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#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H
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#define MMSS_AHB_SRC 0
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#define FAB_AHB_CLK 1
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#define APU_AHB_CLK 2
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#define TV_ENC_AHB_CLK 3
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#define AMP_AHB_CLK 4
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#define DSI2_S_AHB_CLK 5
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#define JPEGD_AHB_CLK 6
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#define GFX2D0_AHB_CLK 7
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#define DSI_S_AHB_CLK 8
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#define DSI2_M_AHB_CLK 9
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#define VPE_AHB_CLK 10
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#define SMMU_AHB_CLK 11
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#define HDMI_M_AHB_CLK 12
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#define VFE_AHB_CLK 13
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#define ROT_AHB_CLK 14
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#define VCODEC_AHB_CLK 15
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#define MDP_AHB_CLK 16
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#define DSI_M_AHB_CLK 17
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#define CSI_AHB_CLK 18
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#define MMSS_IMEM_AHB_CLK 19
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#define IJPEG_AHB_CLK 20
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#define HDMI_S_AHB_CLK 21
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#define GFX3D_AHB_CLK 22
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#define GFX2D1_AHB_CLK 23
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#define MMSS_FPB_CLK 24
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#define MMSS_AXI_SRC 25
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#define MMSS_FAB_CORE 26
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#define FAB_MSP_AXI_CLK 27
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#define JPEGD_AXI_CLK 28
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#define GMEM_AXI_CLK 29
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#define MDP_AXI_CLK 30
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#define MMSS_IMEM_AXI_CLK 31
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#define IJPEG_AXI_CLK 32
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#define GFX3D_AXI_CLK 33
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#define VCODEC_AXI_CLK 34
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#define VFE_AXI_CLK 35
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#define VPE_AXI_CLK 36
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#define ROT_AXI_CLK 37
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#define VCODEC_AXI_A_CLK 38
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#define VCODEC_AXI_B_CLK 39
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#define MM_AXI_S3_FCLK 40
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#define MM_AXI_S2_FCLK 41
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#define MM_AXI_S1_FCLK 42
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#define MM_AXI_S0_FCLK 43
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#define MM_AXI_S2_CLK 44
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#define MM_AXI_S1_CLK 45
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#define MM_AXI_S0_CLK 46
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#define CSI0_SRC 47
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#define CSI0_CLK 48
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#define CSI0_PHY_CLK 49
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#define CSI1_SRC 50
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#define CSI1_CLK 51
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#define CSI1_PHY_CLK 52
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#define CSI2_SRC 53
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#define CSI2_CLK 54
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#define CSI2_PHY_CLK 55
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#define DSI_SRC 56
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#define DSI_CLK 57
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#define CSI_PIX_CLK 58
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#define CSI_RDI_CLK 59
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#define MDP_VSYNC_CLK 60
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#define HDMI_DIV_CLK 61
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#define HDMI_APP_CLK 62
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#define CSI_PIX1_CLK 63
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#define CSI_RDI2_CLK 64
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#define CSI_RDI1_CLK 65
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#define GFX2D0_SRC 66
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#define GFX2D0_CLK 67
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#define GFX2D1_SRC 68
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#define GFX2D1_CLK 69
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#define GFX3D_SRC 70
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#define GFX3D_CLK 71
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#define IJPEG_SRC 72
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#define IJPEG_CLK 73
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#define JPEGD_SRC 74
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#define JPEGD_CLK 75
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#define MDP_SRC 76
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#define MDP_CLK 77
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#define MDP_LUT_CLK 78
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#define DSI2_PIXEL_SRC 79
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#define DSI2_PIXEL_CLK 80
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#define DSI2_SRC 81
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#define DSI2_CLK 82
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#define DSI1_BYTE_SRC 83
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#define DSI1_BYTE_CLK 84
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#define DSI2_BYTE_SRC 85
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#define DSI2_BYTE_CLK 86
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#define DSI1_ESC_SRC 87
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#define DSI1_ESC_CLK 88
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#define DSI2_ESC_SRC 89
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#define DSI2_ESC_CLK 90
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#define ROT_SRC 91
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#define ROT_CLK 92
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#define TV_ENC_CLK 93
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#define TV_DAC_CLK 94
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#define HDMI_TV_CLK 95
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#define MDP_TV_CLK 96
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#define TV_SRC 97
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#define VCODEC_SRC 98
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#define VCODEC_CLK 99
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#define VFE_SRC 100
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#define VFE_CLK 101
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#define VFE_CSI_CLK 102
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#define VPE_SRC 103
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#define VPE_CLK 104
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#define DSI_PIXEL_SRC 105
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#define DSI_PIXEL_CLK 106
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#define CAMCLK0_SRC 107
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#define CAMCLK0_CLK 108
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#define CAMCLK1_SRC 109
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#define CAMCLK1_CLK 110
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#define CAMCLK2_SRC 111
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#define CAMCLK2_CLK 112
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#define CSIPHYTIMER_SRC 113
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#define CSIPHY2_TIMER_CLK 114
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#define CSIPHY1_TIMER_CLK 115
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#define CSIPHY0_TIMER_CLK 116
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#define PLL1 117
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#define PLL2 118
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#define RGB_TV_CLK 119
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#define NPL_TV_CLK 120
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#define VCAP_AHB_CLK 121
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#define VCAP_AXI_CLK 122
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#define VCAP_SRC 123
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#define VCAP_CLK 124
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#define VCAP_NPL_CLK 125
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#define PLL15 126
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#endif
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