linux/drivers/ptp
Jonathan Lemon 1acffc6e09 ptp: ocp: Add timestamp window adjustment
The following process is used to read the PHC clock and correlate
the reading with the "correct" system time.

- get starting timestamp
- issue PCI write command
- issue PCI read command
- get ending timestamp
- read latched sec/nsec registers

The write command is posted to PCI bus and returns.  When the write
arrives at the FPGA, the PHC time is latched into the sec/nsec registers,
and a flag is set indicating the registers are valid.  The read command
returns this flag, and the time retrieval proceeds.

Below is a non-scaled picture of the timing diagram involved.  The
PHC time corresponds to some SYS time between [start, end].  Userspace
usually uses the midpoint between [start, end] to estimate the PCI
delay and match this with the PHC time.

 [start] |                |
   write |-------+        |
	 |        \       |
    read |----+    +----->|
	 |     \          * PHC time latched into register
	 |      \         |
midpoint |       +------->|
	 |                |
	 |                |
	 |           +----|
	 |          /     |
	 |<--------+      |
   [end] |                |

As the diagram indicates, the PHC time is latched before the midpoint,
so the system clock time is slightly off the real PHC time.  This shows
up as a phase error with an oscilliscope.

The workaround here is to provide a tunable which reduces (shrinks)
the end time in the above diagram.  This in turn moves the calculated
midpoint so the system time and PHC time are in agreemment.

Currently, the adjustment reduces the end time by 3/16th of the entire
window.  E.g.:  [start, end] ==> [start, (end - (3/16 * end)], which
produces reasonably good results.

Also reduce delays by just writing to the clock control register
instead of performing a read/modify/write sequence, as the contents
of the control register are known.

Signed-off-by: Jonathan Lemon <jonathan.lemon@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-15 11:10:01 +01:00
..
idt8a340_reg.h ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP 2021-09-14 14:22:12 +01:00
Kconfig ptp: ocp: Simplify Kconfig. 2021-08-26 12:06:42 +01:00
Makefile ptp: add ptp virtual clock driver framework 2021-07-01 13:08:18 -07:00
ptp_chardev.c ptp: only allow phase values lower than 1 period 2020-08-05 12:06:44 -07:00
ptp_clock.c ptp: Relocate lookup cookie to correct block. 2021-07-08 12:33:10 -07:00
ptp_clockmatrix.c ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP 2021-09-14 14:22:12 +01:00
ptp_clockmatrix.h ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP 2021-09-14 14:22:12 +01:00
ptp_dte.c ptp: ptp_dte: use devm_platform_ioremap_resource() to simplify code 2019-10-10 16:21:13 -07:00
ptp_idt82p33.c ptp: idt82p33: optimize _idt82p33_adjfine 2020-11-07 13:10:31 -08:00
ptp_idt82p33.h ptp: idt82p33: use i2c_master_send for bus write 2020-11-07 13:10:27 -08:00
ptp_ines.c ptp: ptp_ines: use new PTP_MSGTYPE_* define(s) 2020-11-23 13:43:39 -08:00
ptp_kvm_arm.c ptp: arm/arm64: Enable ptp_kvm for arm/arm64 2021-04-07 16:33:20 +01:00
ptp_kvm_common.c ptp: Don't print an error if ptp_kvm is not supported 2021-04-20 17:17:55 +01:00
ptp_kvm_x86.c ptp: Reorganize ptp_kvm.c to make it arch-independent 2021-04-07 16:33:07 +01:00
ptp_ocp.c ptp: ocp: Add timestamp window adjustment 2021-09-15 11:10:01 +01:00
ptp_pch.c ptp: ptp_p: Demote non-conformant kernel-doc headers and supply a param description 2021-03-12 17:09:34 -08:00
ptp_private.h ptp: add kernel API ptp_get_vclocks_index() 2021-07-01 13:08:18 -07:00
ptp_qoriq_debugfs.c ptp_qoriq: add little enadian support 2019-02-12 12:58:48 -05:00
ptp_qoriq.c ptp_qoriq: fix overflow in ptp_qoriq_adjfine() u64 calcalation 2021-03-24 12:10:03 -07:00
ptp_sysfs.c ptp: Fix possible memory leak caused by invalid cast 2021-08-08 12:56:41 +01:00
ptp_vclock.c ethernet: fix PTP_1588_CLOCK dependencies 2021-08-13 17:49:05 -07:00
ptp_vmw.c ptp: add VMware virtual PTP clock driver 2020-03-05 17:25:07 -08:00