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In particular, avoid membar instructions in the delay slot of a jmpl instruction. UltraSPARC-I, II, IIi, and IIe have a bug, documented in the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51 The long and short of it is that if the IMU unit misses on a branch or jmpl, and there is a store buffer synchronizing membar in the delay slot, the chip can stop fetching instructions. If interrupts are enabled or some other trap is enabled, the chip will unwedge itself, but performance will suffer. We already had a workaround for this bug in a few spots, but it's better to have the entire tree sanitized for this rule. Signed-off-by: David S. Miller <davem@davemloft.net>
155 lines
2.8 KiB
ArmAsm
155 lines
2.8 KiB
ArmAsm
/* $Id: bitops.S,v 1.3 2001/11/18 00:12:56 davem Exp $
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* bitops.S: Sparc64 atomic bit operations.
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*
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* Copyright (C) 2000 David S. Miller (davem@redhat.com)
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*/
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#include <linux/config.h>
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#include <asm/asi.h>
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.text
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/* On SMP we need to use memory barriers to ensure
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* correct memory operation ordering, nop these out
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* for uniprocessor.
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*/
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#ifdef CONFIG_SMP
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#define BITOP_PRE_BARRIER membar #StoreLoad | #LoadLoad
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#define BITOP_POST_BARRIER \
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ba,pt %xcc, 80b; \
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membar #StoreLoad | #StoreStore
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80: retl
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nop
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#else
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#define BITOP_PRE_BARRIER
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#define BITOP_POST_BARRIER
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#endif
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.globl test_and_set_bit
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.type test_and_set_bit,#function
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test_and_set_bit: /* %o0=nr, %o1=addr */
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BITOP_PRE_BARRIER
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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or %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 1b
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and %g7, %o2, %g2
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clr %o0
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movrne %g2, 1, %o0
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BITOP_POST_BARRIER
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retl
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nop
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.size test_and_set_bit, .-test_and_set_bit
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.globl test_and_clear_bit
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.type test_and_clear_bit,#function
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test_and_clear_bit: /* %o0=nr, %o1=addr */
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BITOP_PRE_BARRIER
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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andn %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 1b
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and %g7, %o2, %g2
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clr %o0
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movrne %g2, 1, %o0
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BITOP_POST_BARRIER
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retl
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nop
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.size test_and_clear_bit, .-test_and_clear_bit
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.globl test_and_change_bit
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.type test_and_change_bit,#function
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test_and_change_bit: /* %o0=nr, %o1=addr */
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BITOP_PRE_BARRIER
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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xor %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 1b
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and %g7, %o2, %g2
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clr %o0
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movrne %g2, 1, %o0
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BITOP_POST_BARRIER
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retl
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nop
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.size test_and_change_bit, .-test_and_change_bit
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.globl set_bit
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.type set_bit,#function
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set_bit: /* %o0=nr, %o1=addr */
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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or %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 1b
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nop
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retl
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nop
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.size set_bit, .-set_bit
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.globl clear_bit
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.type clear_bit,#function
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clear_bit: /* %o0=nr, %o1=addr */
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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andn %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 1b
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nop
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retl
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nop
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.size clear_bit, .-clear_bit
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.globl change_bit
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.type change_bit,#function
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change_bit: /* %o0=nr, %o1=addr */
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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xor %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 1b
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nop
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retl
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nop
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.size change_bit, .-change_bit
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