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It was x86 specific and imcomplete at that, improve the situation by making it clear where the example provided applies and by adding the URLs for the Intel and AMD manuals where this is discussed in depth. Acked-by: Robert Richter <robert.richter@amd.com> Cc: Cyrill Gorcunov <gorcunov@gmail.com> Cc: Frédéric Weisbecker <fweisbec@gmail.com> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Tom Zanussi <tzanussi@gmail.com> Cc: Robert Richter <robert.richter@amd.com> Reported-by: Robert Richter <robert.richter@amd.com LKML-Reference: <new-submission> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
57 lines
1.9 KiB
Plaintext
57 lines
1.9 KiB
Plaintext
perf-list(1)
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============
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NAME
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----
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perf-list - List all symbolic event types
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SYNOPSIS
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--------
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[verse]
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'perf list'
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DESCRIPTION
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-----------
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This command displays the symbolic event types which can be selected in the
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various perf commands with the -e option.
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RAW HARDWARE EVENT DESCRIPTOR
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-----------------------------
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Even when an event is not available in a symbolic form within perf right now,
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it can be encoded in a per processor specific way.
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For instance For x86 CPUs NNN represents the raw register encoding with the
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layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
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of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
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Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
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Example:
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If the Intel docs for a QM720 Core i7 describe an event as:
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Event Umask Event Mask
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Num. Value Mnemonic Description Comment
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A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
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delivered by loop stream detector invert to count
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cycles
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raw encoding of 0x1A8 can be used:
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perf stat -e r1a8 -a sleep 1
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perf record -e r1a8 ...
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You should refer to the processor specific documentation for getting these
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details. Some of them are referenced in the SEE ALSO section below.
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OPTIONS
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-------
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None
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SEE ALSO
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--------
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linkperf:perf-stat[1], linkperf:perf-top[1],
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linkperf:perf-record[1],
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http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
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http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
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