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Add tcc cooling support for the AlderLake platform. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20210809115635.10100-1-sumeet.r.pawnikar@intel.com
132 lines
2.8 KiB
C
132 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* cooling device driver that activates the processor throttling by
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* programming the TCC Offset register.
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* Copyright (c) 2021, Intel Corporation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/thermal.h>
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#include <asm/cpu_device_id.h>
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#define TCC_SHIFT 24
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#define TCC_MASK (0x3fULL<<24)
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#define TCC_PROGRAMMABLE BIT(30)
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static struct thermal_cooling_device *tcc_cdev;
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static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long
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*state)
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{
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*state = TCC_MASK >> TCC_SHIFT;
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return 0;
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}
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static int tcc_offset_update(int tcc)
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{
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u64 val;
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int err;
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err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val);
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if (err)
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return err;
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val &= ~TCC_MASK;
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val |= tcc << TCC_SHIFT;
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err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val);
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if (err)
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return err;
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return 0;
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}
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static int tcc_get_cur_state(struct thermal_cooling_device *cdev, unsigned long
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*state)
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{
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u64 val;
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int err;
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err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val);
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if (err)
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return err;
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*state = (val & TCC_MASK) >> TCC_SHIFT;
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return 0;
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}
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static int tcc_set_cur_state(struct thermal_cooling_device *cdev, unsigned long
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state)
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{
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return tcc_offset_update(state);
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}
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static const struct thermal_cooling_device_ops tcc_cooling_ops = {
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.get_max_state = tcc_get_max_state,
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.get_cur_state = tcc_get_cur_state,
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.set_cur_state = tcc_set_cur_state,
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};
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static const struct x86_cpu_id tcc_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, tcc_ids);
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static int __init tcc_cooling_init(void)
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{
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int ret;
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u64 val;
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const struct x86_cpu_id *id;
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int err;
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id = x86_match_cpu(tcc_ids);
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if (!id)
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return -ENODEV;
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err = rdmsrl_safe(MSR_PLATFORM_INFO, &val);
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if (err)
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return err;
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if (!(val & TCC_PROGRAMMABLE))
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return -ENODEV;
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pr_info("Programmable TCC Offset detected\n");
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tcc_cdev =
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thermal_cooling_device_register("TCC Offset", NULL,
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&tcc_cooling_ops);
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if (IS_ERR(tcc_cdev)) {
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ret = PTR_ERR(tcc_cdev);
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return ret;
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}
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return 0;
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}
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module_init(tcc_cooling_init)
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static void __exit tcc_cooling_exit(void)
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{
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thermal_cooling_device_unregister(tcc_cdev);
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}
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module_exit(tcc_cooling_exit)
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MODULE_DESCRIPTION("TCC offset cooling device Driver");
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MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
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MODULE_LICENSE("GPL v2");
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