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18aecc2b64
This support was partially present in the existing code (look for "__tilegx__" ifdefs) but with this change you can build a working kernel using the TILE-Gx toolchain and ARCH=tilegx. Most of these files are new, generally adding a foo_64.c file where previously there was just a foo_32.c file. The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx, using the existing SRCARCH mechanism in the top-level Makefile. Changes to existing files: - <asm/bitops.h> and <asm/bitops_32.h> changed to factor the include of <asm-generic/bitops/non-atomic.h> in the common header. - <asm/compat.h> and arch/tile/kernel/compat.c changed to remove the "const" markers I had put on compat_sys_execve() when trying to match some recent similar changes to the non-compat execve. It turns out the compat version wasn't "upgraded" to use const. - <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were previously included accidentally, with the 32-bit contents. Now they have the proper 64-bit contents. Finally, I had to hack the existing hacky drivers/input/input-compat.h to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64). Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
87 lines
2.5 KiB
C
87 lines
2.5 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* Do memcpy(), but trap and return "n" when a load or store faults.
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*
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* Note: this idiom only works when memcpy() compiles to a leaf function.
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* If "sp" is updated during memcpy, the "jrp lr" will be incorrect.
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*
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* Also note that we are capturing "n" from the containing scope here.
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*/
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#define _ST(p, inst, v) \
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({ \
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asm("1: " #inst " %0, %1;" \
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".pushsection .coldtext.memcpy,\"ax\";" \
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"2: { move r0, %2; jrp lr };" \
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".section __ex_table,\"a\";" \
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".quad 1b, 2b;" \
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".popsection" \
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: "=m" (*(p)) : "r" (v), "r" (n)); \
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})
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#define _LD(p, inst) \
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({ \
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unsigned long __v; \
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asm("1: " #inst " %0, %1;" \
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".pushsection .coldtext.memcpy,\"ax\";" \
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"2: { move r0, %2; jrp lr };" \
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".section __ex_table,\"a\";" \
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".quad 1b, 2b;" \
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".popsection" \
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: "=r" (__v) : "m" (*(p)), "r" (n)); \
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__v; \
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})
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#define USERCOPY_FUNC __copy_to_user_inatomic
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#define ST1(p, v) _ST((p), st1, (v))
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#define ST2(p, v) _ST((p), st2, (v))
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#define ST4(p, v) _ST((p), st4, (v))
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#define ST8(p, v) _ST((p), st, (v))
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#define LD1 LD
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#define LD2 LD
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#define LD4 LD
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#define LD8 LD
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#include "memcpy_64.c"
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#define USERCOPY_FUNC __copy_from_user_inatomic
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#define ST1 ST
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#define ST2 ST
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#define ST4 ST
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#define ST8 ST
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#define LD1(p) _LD((p), ld1u)
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#define LD2(p) _LD((p), ld2u)
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#define LD4(p) _LD((p), ld4u)
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#define LD8(p) _LD((p), ld)
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#include "memcpy_64.c"
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#define USERCOPY_FUNC __copy_in_user_inatomic
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#define ST1(p, v) _ST((p), st1, (v))
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#define ST2(p, v) _ST((p), st2, (v))
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#define ST4(p, v) _ST((p), st4, (v))
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#define ST8(p, v) _ST((p), st, (v))
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#define LD1(p) _LD((p), ld1u)
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#define LD2(p) _LD((p), ld2u)
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#define LD4(p) _LD((p), ld4u)
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#define LD8(p) _LD((p), ld)
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#include "memcpy_64.c"
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unsigned long __copy_from_user_zeroing(void *to, const void __user *from,
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unsigned long n)
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{
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unsigned long rc = __copy_from_user_inatomic(to, from, n);
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if (unlikely(rc))
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memset(to + n - rc, 0, rc);
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return rc;
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}
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