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c97006046c
The per-device CDAT data provides performance data that is relevant for mapping which CXL devices can participate in which CXL ranges by QTG (QoS Throttling Group) (per ECN: CXL 2.0 CEDT CFMWS & QTG_DSM) [1]. The QTG association specified in the ECN is advisory. Until the cxl_acpi driver grows support for invoking the QTG _DSM method the CDAT data is only of interest to userspace that may need it for debug purposes. Search the DOE mailboxes available, query CDAT data, cache the data and make it available via a sysfs binary attribute per endpoint at: /sys/bus/cxl/devices/endpointX/CDAT ...similar to other ACPI-structured table data in /sys/firmware/ACPI/tables. The CDAT is relative to 'struct cxl_port' objects since switches in addition to endpoints can host a CDAT instance. Switch CDAT support is not implemented. This does not support table updates at runtime. It will always provide whatever was there when first cached. It is also the case that table updates are not expected outside of explicit DPA address map affecting commands like Set Partition with the immediate flag set. Given that the driver does not support Set Partition with the immediate flag set there is no current need for update support. Link: https://www.computeexpresslink.org/spec-landing [1] Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> [djbw: drop in-kernel parsing infra for now, and other minor fixups] Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220719205249.566684-7-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_PCI_H__
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#define __CXL_PCI_H__
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#include <linux/pci.h>
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#include "cxl.h"
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#define CXL_MEMORY_PROGIF 0x10
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/*
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* See section 8.1 Configuration Space Registers in the CXL 2.0
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* Specification. Names are taken straight from the specification with "CXL" and
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* "DVSEC" redundancies removed. When obvious, abbreviations may be used.
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*/
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#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
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#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
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/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
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#define CXL_DVSEC_PCIE_DEVICE 0
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#define CXL_DVSEC_CAP_OFFSET 0xA
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#define CXL_DVSEC_MEM_CAPABLE BIT(2)
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#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4)
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#define CXL_DVSEC_CTRL_OFFSET 0xC
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#define CXL_DVSEC_MEM_ENABLE BIT(2)
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#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
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#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
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#define CXL_DVSEC_MEM_INFO_VALID BIT(0)
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#define CXL_DVSEC_MEM_ACTIVE BIT(1)
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#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28)
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#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
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#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
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#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28)
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/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
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#define CXL_DVSEC_FUNCTION_MAP 2
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/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
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#define CXL_DVSEC_PORT_EXTENSIONS 3
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/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
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#define CXL_DVSEC_PORT_GPF 4
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/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
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#define CXL_DVSEC_DEVICE_GPF 5
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/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
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#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7
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/* CXL 2.0 8.1.9: Register Locator DVSEC */
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#define CXL_DVSEC_REG_LOCATOR 8
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#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
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#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16)
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/* Register Block Identifier (RBI) */
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enum cxl_regloc_type {
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CXL_REGLOC_RBI_EMPTY = 0,
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CXL_REGLOC_RBI_COMPONENT,
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CXL_REGLOC_RBI_VIRT,
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CXL_REGLOC_RBI_MEMDEV,
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CXL_REGLOC_RBI_TYPES
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};
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static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
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struct cxl_register_map *map)
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{
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if (map->block_offset == U64_MAX)
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return CXL_RESOURCE_NONE;
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return pci_resource_start(pdev, map->barno) + map->block_offset;
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}
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int devm_cxl_port_enumerate_dports(struct cxl_port *port);
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struct cxl_dev_state;
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int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
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void read_cdat_data(struct cxl_port *port);
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#endif /* __CXL_PCI_H__ */
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