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The final icache_flush was in the update_mmu_cache, and update_mmu_cache is after the set_pte_at. Thus, when CPU0 sets the pte, the other CPU would see it before the icache_flush broadcast happens, and their icaches may have cached stale VIPT cache lines in their I-caches. When address translation was ready for the new cache line, they will use the stale data of icache, not the fresh one of the dcache. The csky instruction cache is VIPT, and it needs an origin virtual address to invalidate the virtual address index entries of cache ways. The current implementation uses a temporary mapping mechanism - kmap_atomic, which returns a new virtual address for invalidation. But, the original virtual address cache line may still in the I-cache. So force invalidation I-cache in update_mmu_cache, and prevent flush_dcache when there is an EXEC page. This bug was detected in the 4*c860 SMP system, and this patch could pass the stress test. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> |
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