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13079a7333
we will select now the DBGU used by the soc at Kconfig level For the DEBUG_LL and early_printk this will allow to select which DBGU to use this will also allow to select them when multiple SOC are enabled Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
314 lines
7.6 KiB
C
314 lines
7.6 KiB
C
/*
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* Copyright (C) 2007 Atmel Corporation.
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Under GPLv2
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/pm.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_shdwc.h>
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#include "soc.h"
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#include "generic.h"
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struct at91_init_soc __initdata at91_boot_soc;
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struct at91_socinfo at91_soc_initdata;
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EXPORT_SYMBOL(at91_soc_initdata);
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void __init at91rm9200_set_type(int type)
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{
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if (type == ARCH_REVISON_9200_PQFP)
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at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
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else
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at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
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}
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void __init at91_init_irq_default(void)
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{
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at91_init_interrupts(at91_boot_soc.default_irq_priority);
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}
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void __init at91_init_interrupts(unsigned int *priority)
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{
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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}
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static struct map_desc sram_desc[2] __initdata;
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void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
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{
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struct map_desc *desc = &sram_desc[bank];
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desc->virtual = AT91_IO_VIRT_BASE - length;
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if (bank > 0)
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desc->virtual -= sram_desc[bank - 1].length;
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desc->pfn = __phys_to_pfn(base);
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desc->length = length;
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desc->type = MT_DEVICE;
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pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
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base, length, desc->virtual);
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iotable_init(desc, 1);
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}
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static struct map_desc at91_io_desc __initdata = {
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.virtual = AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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};
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void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type)
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{
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if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1))
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return (void __iomem *)AT91_IO_P2V(p);
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return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
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}
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EXPORT_SYMBOL(at91_ioremap);
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void at91_iounmap(volatile void __iomem *addr)
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{
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unsigned long virt = (unsigned long)addr;
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if (virt >= VMALLOC_START && virt < VMALLOC_END)
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__iounmap(addr);
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}
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EXPORT_SYMBOL(at91_iounmap);
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static void __init soc_detect(u32 dbgu_base)
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{
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u32 cidr, socid;
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cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
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socid = cidr & ~AT91_CIDR_VERSION;
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switch (socid) {
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case ARCH_ID_AT91CAP9: {
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#ifdef CONFIG_AT91_PMC_UNIT
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u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
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if (pmc_ver == ARCH_REVISION_CAP9_B)
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at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
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else if (pmc_ver == ARCH_REVISION_CAP9_C)
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at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
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#endif
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at91_soc_initdata.type = AT91_SOC_CAP9;
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at91_boot_soc = at91cap9_soc;
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break;
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}
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case ARCH_ID_AT91RM9200:
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at91_soc_initdata.type = AT91_SOC_RM9200;
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at91_boot_soc = at91rm9200_soc;
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break;
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case ARCH_ID_AT91SAM9260:
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at91_soc_initdata.type = AT91_SOC_SAM9260;
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at91_boot_soc = at91sam9260_soc;
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break;
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case ARCH_ID_AT91SAM9261:
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at91_soc_initdata.type = AT91_SOC_SAM9261;
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at91_boot_soc = at91sam9261_soc;
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break;
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case ARCH_ID_AT91SAM9263:
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at91_soc_initdata.type = AT91_SOC_SAM9263;
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at91_boot_soc = at91sam9263_soc;
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break;
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case ARCH_ID_AT91SAM9G20:
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at91_soc_initdata.type = AT91_SOC_SAM9G20;
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at91_boot_soc = at91sam9260_soc;
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break;
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case ARCH_ID_AT91SAM9G45:
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at91_soc_initdata.type = AT91_SOC_SAM9G45;
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if (cidr == ARCH_ID_AT91SAM9G45ES)
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at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
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at91_boot_soc = at91sam9g45_soc;
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break;
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case ARCH_ID_AT91SAM9RL64:
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at91_soc_initdata.type = AT91_SOC_SAM9RL;
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at91_boot_soc = at91sam9rl_soc;
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break;
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case ARCH_ID_AT91SAM9X5:
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at91_soc_initdata.type = AT91_SOC_SAM9X5;
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at91_boot_soc = at91sam9x5_soc;
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break;
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}
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/* at91sam9g10 */
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if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
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at91_soc_initdata.type = AT91_SOC_SAM9G10;
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at91_boot_soc = at91sam9261_soc;
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}
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/* at91sam9xe */
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else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
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at91_soc_initdata.type = AT91_SOC_SAM9260;
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at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
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at91_boot_soc = at91sam9260_soc;
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}
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if (!at91_soc_is_detected())
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return;
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at91_soc_initdata.cidr = cidr;
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/* sub version of soc */
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at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
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if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
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switch (at91_soc_initdata.exid) {
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case ARCH_EXID_AT91SAM9M10:
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at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
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break;
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case ARCH_EXID_AT91SAM9G46:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
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break;
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case ARCH_EXID_AT91SAM9M11:
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at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
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break;
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}
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}
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if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
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switch (at91_soc_initdata.exid) {
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case ARCH_EXID_AT91SAM9G15:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
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break;
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case ARCH_EXID_AT91SAM9G35:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
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break;
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case ARCH_EXID_AT91SAM9X35:
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at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
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break;
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case ARCH_EXID_AT91SAM9G25:
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at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
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break;
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case ARCH_EXID_AT91SAM9X25:
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at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
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break;
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}
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}
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}
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static const char *soc_name[] = {
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[AT91_SOC_RM9200] = "at91rm9200",
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[AT91_SOC_CAP9] = "at91cap9",
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[AT91_SOC_SAM9260] = "at91sam9260",
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[AT91_SOC_SAM9261] = "at91sam9261",
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[AT91_SOC_SAM9263] = "at91sam9263",
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[AT91_SOC_SAM9G10] = "at91sam9g10",
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[AT91_SOC_SAM9G20] = "at91sam9g20",
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[AT91_SOC_SAM9G45] = "at91sam9g45",
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[AT91_SOC_SAM9RL] = "at91sam9rl",
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[AT91_SOC_SAM9X5] = "at91sam9x5",
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[AT91_SOC_NONE] = "Unknown"
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};
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const char *at91_get_soc_type(struct at91_socinfo *c)
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{
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return soc_name[c->type];
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}
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EXPORT_SYMBOL(at91_get_soc_type);
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static const char *soc_subtype_name[] = {
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[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
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[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
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[AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
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[AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
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[AT91_SOC_SAM9XE] = "at91sam9xe",
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[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
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[AT91_SOC_SAM9M10] = "at91sam9m10",
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[AT91_SOC_SAM9G46] = "at91sam9g46",
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[AT91_SOC_SAM9M11] = "at91sam9m11",
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[AT91_SOC_SAM9G15] = "at91sam9g15",
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[AT91_SOC_SAM9G35] = "at91sam9g35",
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[AT91_SOC_SAM9X35] = "at91sam9x35",
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[AT91_SOC_SAM9G25] = "at91sam9g25",
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[AT91_SOC_SAM9X25] = "at91sam9x25",
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[AT91_SOC_SUBTYPE_NONE] = "Unknown"
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};
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const char *at91_get_soc_subtype(struct at91_socinfo *c)
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{
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return soc_subtype_name[c->subtype];
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}
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EXPORT_SYMBOL(at91_get_soc_subtype);
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void __init at91_map_io(void)
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{
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/* Map peripherals */
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iotable_init(&at91_io_desc, 1);
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at91_soc_initdata.type = AT91_SOC_NONE;
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at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
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soc_detect(AT91_BASE_DBGU0);
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if (!at91_soc_is_detected())
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soc_detect(AT91_BASE_DBGU1);
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if (!at91_soc_is_detected())
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panic("AT91: Impossible to detect the SOC type");
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pr_info("AT91: Detected soc type: %s\n",
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at91_get_soc_type(&at91_soc_initdata));
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pr_info("AT91: Detected soc subtype: %s\n",
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at91_get_soc_subtype(&at91_soc_initdata));
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if (!at91_soc_is_enabled())
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panic("AT91: Soc not enabled");
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if (at91_boot_soc.map_io)
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at91_boot_soc.map_io();
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}
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void __iomem *at91_shdwc_base = NULL;
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static void at91sam9_poweroff(void)
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{
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at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
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}
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void __init at91_ioremap_shdwc(u32 base_addr)
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{
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at91_shdwc_base = ioremap(base_addr, 16);
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if (!at91_shdwc_base)
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panic("Impossible to ioremap at91_shdwc_base\n");
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pm_power_off = at91sam9_poweroff;
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}
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void __init at91_initialize(unsigned long main_clock)
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{
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at91_boot_soc.ioremap_registers();
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91_boot_soc.register_clocks();
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at91_boot_soc.init();
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}
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