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11e5a202ca
Fix indentation and blank/tab issues. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
337 lines
11 KiB
C
337 lines
11 KiB
C
/*****************************************************************************
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* *
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* File: espi.c *
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* $Revision: 1.14 $ *
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* $Date: 2005/05/14 00:59:32 $ *
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* Description: *
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* Ethernet SPI functionality. *
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* part of the Chelsio 10Gb Ethernet Driver. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License, version 2, as *
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* published by the Free Software Foundation. *
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* *
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* You should have received a copy of the GNU General Public License along *
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* with this program; if not, write to the Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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* *
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* http://www.chelsio.com *
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* *
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* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
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* All rights reserved. *
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* *
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* Maintainers: maintainers@chelsio.com *
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* *
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* Authors: Dimitrios Michailidis <dm@chelsio.com> *
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* Tina Yang <tainay@chelsio.com> *
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* Felix Marti <felix@chelsio.com> *
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* Scott Bardone <sbardone@chelsio.com> *
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* Kurt Ottaway <kottaway@chelsio.com> *
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* Frank DiMambro <frank@chelsio.com> *
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* *
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* History: *
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* *
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****************************************************************************/
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#include "common.h"
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#include "regs.h"
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#include "espi.h"
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struct peespi {
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adapter_t *adapter;
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struct espi_intr_counts intr_cnt;
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u32 misc_ctrl;
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spinlock_t lock;
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};
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#define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \
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F_RAMPARITYERR | F_DIP2PARITYERR)
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#define MON_MASK (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \
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| F_MONITORED_INTERFACE)
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#define TRICN_CNFG 14
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#define TRICN_CMD_READ 0x11
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#define TRICN_CMD_WRITE 0x21
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#define TRICN_CMD_ATTEMPTS 10
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static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
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int ch_addr, int reg_offset, u32 wr_data)
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{
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int busy, attempts = TRICN_CMD_ATTEMPTS;
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writel(V_WRITE_DATA(wr_data) |
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V_REGISTER_OFFSET(reg_offset) |
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V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
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V_BUNDLE_ADDR(bundle_addr) |
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V_SPI4_COMMAND(TRICN_CMD_WRITE),
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adapter->regs + A_ESPI_CMD_ADDR);
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writel(0, adapter->regs + A_ESPI_GOSTAT);
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do {
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busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
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} while (busy && --attempts);
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if (busy)
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CH_ERR("%s: TRICN write timed out\n", adapter->name);
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return busy;
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}
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/* 1. Deassert rx_reset_core. */
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/* 2. Program TRICN_CNFG registers. */
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/* 3. Deassert rx_reset_link */
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static int tricn_init(adapter_t *adapter)
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{
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int i = 0;
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int stat = 0;
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int timeout = 0;
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int is_ready = 0;
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/* 1 */
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timeout=1000;
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do {
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stat = readl(adapter->regs + A_ESPI_RX_RESET);
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is_ready = (stat & 0x4);
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timeout--;
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udelay(5);
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} while (!is_ready || (timeout==0));
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writel(0x2, adapter->regs + A_ESPI_RX_RESET);
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if (timeout==0)
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{
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CH_ERR("ESPI : ERROR : Timeout tricn_init() \n");
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t1_fatal_err(adapter);
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}
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/* 2 */
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tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
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tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
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tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
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for (i=1; i<= 8; i++) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
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for (i=1; i<= 2; i++) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
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for (i=1; i<= 3; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
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for (i=4; i<= 4; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
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for (i=5; i<= 5; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
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for (i=6; i<= 6; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
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for (i=7; i<= 7; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0x80);
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for (i=8; i<= 8; i++) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xf1);
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/* 3 */
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writel(0x3, adapter->regs + A_ESPI_RX_RESET);
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return 0;
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}
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void t1_espi_intr_enable(struct peespi *espi)
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{
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u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
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/*
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* Cannot enable ESPI interrupts on T1B because HW asserts the
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* interrupt incorrectly, namely the driver gets ESPI interrupts
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* but no data is actually dropped (can verify this reading the ESPI
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* drop registers). Also, once the ESPI interrupt is asserted it
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* cannot be cleared (HW bug).
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*/
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enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
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writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
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writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
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}
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void t1_espi_intr_clear(struct peespi *espi)
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{
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writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
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writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
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}
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void t1_espi_intr_disable(struct peespi *espi)
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{
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u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
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writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
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writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
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}
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int t1_espi_intr_handler(struct peespi *espi)
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{
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u32 cnt;
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u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
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if (status & F_DIP4ERR)
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espi->intr_cnt.DIP4_err++;
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if (status & F_RXDROP)
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espi->intr_cnt.rx_drops++;
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if (status & F_TXDROP)
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espi->intr_cnt.tx_drops++;
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if (status & F_RXOVERFLOW)
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espi->intr_cnt.rx_ovflw++;
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if (status & F_RAMPARITYERR)
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espi->intr_cnt.parity_err++;
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if (status & F_DIP2PARITYERR) {
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espi->intr_cnt.DIP2_parity_err++;
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/*
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* Must read the error count to clear the interrupt
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* that it causes.
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*/
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cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
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}
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/*
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* For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
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* write the status as is.
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*/
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if (status && t1_is_T1B(espi->adapter))
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status = 1;
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writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
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return 0;
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}
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const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
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{
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return &espi->intr_cnt;
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}
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static void espi_setup_for_pm3393(adapter_t *adapter)
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{
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u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
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writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
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writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
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writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
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writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
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writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
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writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
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writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
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writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
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writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
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}
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/* T2 Init part -- */
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/* 1. Set T_ESPI_MISCCTRL_ADDR */
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/* 2. Init ESPI registers. */
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/* 3. Init TriCN Hard Macro */
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int t1_espi_init(struct peespi *espi, int mac_type, int nports)
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{
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u32 cnt;
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u32 status_enable_extra = 0;
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adapter_t *adapter = espi->adapter;
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u32 status, burstval = 0x800100;
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/* Disable ESPI training. MACs that can handle it enable it below. */
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writel(0, adapter->regs + A_ESPI_TRAIN);
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if (is_T2(adapter)) {
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writel(V_OUT_OF_SYNC_COUNT(4) |
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V_DIP2_PARITY_ERR_THRES(3) |
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V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
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if (nports == 4) {
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/* T204: maxburst1 = 0x40, maxburst2 = 0x20 */
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burstval = 0x200040;
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}
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}
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writel(burstval, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
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switch (mac_type) {
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case CHBT_MAC_PM3393:
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espi_setup_for_pm3393(adapter);
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break;
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default:
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return -1;
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}
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/*
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* Make sure any pending interrupts from the SPI are
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* Cleared before enabling the interrupt.
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*/
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writel(ESPI_INTR_MASK, espi->adapter->regs + A_ESPI_INTR_ENABLE);
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status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
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if (status & F_DIP2PARITYERR) {
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cnt = readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
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}
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/*
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* For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
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* write the status as is.
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*/
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if (status && t1_is_T1B(espi->adapter))
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status = 1;
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writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
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writel(status_enable_extra | F_RXSTATUSENABLE,
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adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
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if (is_T2(adapter)) {
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tricn_init(adapter);
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/*
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* Always position the control at the 1st port egress IN
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* (sop,eop) counter to reduce PIOs for T/N210 workaround.
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*/
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espi->misc_ctrl = (readl(adapter->regs + A_ESPI_MISC_CONTROL)
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& ~MON_MASK) | (F_MONITORED_DIRECTION
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| F_MONITORED_INTERFACE);
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writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
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spin_lock_init(&espi->lock);
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}
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return 0;
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}
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void t1_espi_destroy(struct peespi *espi)
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{
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kfree(espi);
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}
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struct peespi *t1_espi_create(adapter_t *adapter)
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{
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struct peespi *espi = kzalloc(sizeof(*espi), GFP_KERNEL);
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if (espi)
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espi->adapter = adapter;
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return espi;
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}
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void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
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{
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struct peespi *espi = adapter->espi;
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if (!is_T2(adapter))
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return;
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spin_lock(&espi->lock);
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espi->misc_ctrl = (val & ~MON_MASK) |
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(espi->misc_ctrl & MON_MASK);
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writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
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spin_unlock(&espi->lock);
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}
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u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
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{
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u32 sel;
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struct peespi *espi = adapter->espi;
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if (!is_T2(adapter))
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return 0;
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sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
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if (!wait) {
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if (!spin_trylock(&espi->lock))
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return 0;
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}
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else
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spin_lock(&espi->lock);
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if ((sel != (espi->misc_ctrl & MON_MASK))) {
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writel(((espi->misc_ctrl & ~MON_MASK) | sel),
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adapter->regs + A_ESPI_MISC_CONTROL);
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sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
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writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
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}
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else
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sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
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spin_unlock(&espi->lock);
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return sel;
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}
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