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e5a7431f5a
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins). The hwirq base for each sgpio bank should be multiples of 64 rather than multiples of 32. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
613 lines
15 KiB
C
613 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2019 American Megatrends International LLC.
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*
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* Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/hashtable.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#define ASPEED_SGPIO_CTRL 0x54
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#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
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#define ASPEED_SGPIO_ENABLE BIT(0)
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#define ASPEED_SGPIO_PINS_SHIFT 6
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struct aspeed_sgpio_pdata {
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const u32 pin_mask;
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};
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struct aspeed_sgpio {
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struct gpio_chip chip;
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struct irq_chip intc;
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struct clk *pclk;
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spinlock_t lock;
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void __iomem *base;
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int irq;
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};
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struct aspeed_sgpio_bank {
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u16 val_regs;
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u16 rdata_reg;
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u16 irq_regs;
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u16 tolerance_regs;
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const char names[4][3];
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};
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/*
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* Note: The "value" register returns the input value when the GPIO is
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* configured as an input.
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*
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* The "rdata" register returns the output value when the GPIO is
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* configured as an output.
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*/
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static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
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{
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.val_regs = 0x0000,
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.rdata_reg = 0x0070,
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.irq_regs = 0x0004,
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.tolerance_regs = 0x0018,
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.names = { "A", "B", "C", "D" },
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},
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{
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.val_regs = 0x001C,
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.rdata_reg = 0x0074,
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.irq_regs = 0x0020,
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.tolerance_regs = 0x0034,
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.names = { "E", "F", "G", "H" },
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},
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{
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.val_regs = 0x0038,
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.rdata_reg = 0x0078,
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.irq_regs = 0x003C,
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.tolerance_regs = 0x0050,
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.names = { "I", "J", "K", "L" },
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},
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{
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.val_regs = 0x0090,
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.rdata_reg = 0x007C,
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.irq_regs = 0x0094,
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.tolerance_regs = 0x00A8,
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.names = { "M", "N", "O", "P" },
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},
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};
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enum aspeed_sgpio_reg {
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reg_val,
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reg_rdata,
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reg_irq_enable,
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reg_irq_type0,
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reg_irq_type1,
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reg_irq_type2,
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reg_irq_status,
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reg_tolerance,
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};
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#define GPIO_VAL_VALUE 0x00
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#define GPIO_IRQ_ENABLE 0x00
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#define GPIO_IRQ_TYPE0 0x04
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#define GPIO_IRQ_TYPE1 0x08
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#define GPIO_IRQ_TYPE2 0x0C
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#define GPIO_IRQ_STATUS 0x10
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static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
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const struct aspeed_sgpio_bank *bank,
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const enum aspeed_sgpio_reg reg)
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{
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switch (reg) {
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case reg_val:
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return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
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case reg_rdata:
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return gpio->base + bank->rdata_reg;
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case reg_irq_enable:
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return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
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case reg_irq_type0:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
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case reg_irq_type1:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
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case reg_irq_type2:
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return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
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case reg_irq_status:
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return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
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case reg_tolerance:
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return gpio->base + bank->tolerance_regs;
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default:
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/* acturally if code runs to here, it's an error case */
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BUG();
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}
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}
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#define GPIO_BANK(x) ((x) >> 6)
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#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
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#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
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static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank;
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bank = GPIO_BANK(offset);
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WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
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return &aspeed_sgpio_banks[bank];
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}
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static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask, unsigned int ngpios)
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{
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bitmap_set(valid_mask, 0, ngpios);
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return 0;
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}
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static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask, unsigned int ngpios)
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{
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unsigned int i;
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/* input GPIOs are even bits */
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for (i = 0; i < ngpios; i++) {
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if (i % 2)
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clear_bit(i, valid_mask);
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}
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}
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static bool aspeed_sgpio_is_input(unsigned int offset)
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{
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return !(offset % 2);
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}
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static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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unsigned long flags;
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enum aspeed_sgpio_reg reg;
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int rc = 0;
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spin_lock_irqsave(&gpio->lock, flags);
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reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
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rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
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spin_unlock_irqrestore(&gpio->lock, flags);
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return rc;
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}
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static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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void __iomem *addr_r, *addr_w;
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u32 reg = 0;
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if (aspeed_sgpio_is_input(offset))
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return -EINVAL;
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/* Since this is an output, read the cached value from rdata, then
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* update val. */
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addr_r = bank_reg(gpio, bank, reg_rdata);
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addr_w = bank_reg(gpio, bank, reg_val);
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reg = ioread32(addr_r);
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if (val)
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reg |= GPIO_BIT(offset);
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else
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reg &= ~GPIO_BIT(offset);
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iowrite32(reg, addr_w);
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return 0;
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}
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static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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sgpio_set_value(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
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}
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static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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int rc;
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/* No special action is required for setting the direction; we'll
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* error-out in sgpio_set_value if this isn't an output GPIO */
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spin_lock_irqsave(&gpio->lock, flags);
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rc = sgpio_set_value(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return rc;
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}
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static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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return !!aspeed_sgpio_is_input(offset);
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}
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static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
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struct aspeed_sgpio **gpio,
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const struct aspeed_sgpio_bank **bank,
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u32 *bit, int *offset)
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{
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struct aspeed_sgpio *internal;
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*offset = irqd_to_hwirq(d);
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internal = irq_data_get_irq_chip_data(d);
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WARN_ON(!internal);
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*gpio = internal;
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*bank = to_bank(*offset);
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*bit = GPIO_BIT(*offset);
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}
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static void aspeed_sgpio_irq_ack(struct irq_data *d)
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{
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const struct aspeed_sgpio_bank *bank;
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struct aspeed_sgpio *gpio;
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unsigned long flags;
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void __iomem *status_addr;
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int offset;
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u32 bit;
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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status_addr = bank_reg(gpio, bank, reg_irq_status);
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spin_lock_irqsave(&gpio->lock, flags);
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iowrite32(bit, status_addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
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{
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const struct aspeed_sgpio_bank *bank;
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struct aspeed_sgpio *gpio;
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unsigned long flags;
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u32 reg, bit;
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void __iomem *addr;
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int offset;
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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addr = bank_reg(gpio, bank, reg_irq_enable);
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spin_lock_irqsave(&gpio->lock, flags);
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reg = ioread32(addr);
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if (set)
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reg |= bit;
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else
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reg &= ~bit;
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iowrite32(reg, addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void aspeed_sgpio_irq_mask(struct irq_data *d)
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{
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aspeed_sgpio_irq_set_mask(d, false);
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}
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static void aspeed_sgpio_irq_unmask(struct irq_data *d)
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{
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aspeed_sgpio_irq_set_mask(d, true);
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}
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static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
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{
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u32 type0 = 0;
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u32 type1 = 0;
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u32 type2 = 0;
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u32 bit, reg;
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const struct aspeed_sgpio_bank *bank;
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irq_flow_handler_t handler;
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struct aspeed_sgpio *gpio;
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unsigned long flags;
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void __iomem *addr;
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int offset;
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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type2 |= bit;
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fallthrough;
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case IRQ_TYPE_EDGE_RISING:
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type0 |= bit;
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fallthrough;
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case IRQ_TYPE_EDGE_FALLING:
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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type0 |= bit;
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fallthrough;
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case IRQ_TYPE_LEVEL_LOW:
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type1 |= bit;
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handler = handle_level_irq;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&gpio->lock, flags);
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addr = bank_reg(gpio, bank, reg_irq_type0);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type0;
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iowrite32(reg, addr);
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addr = bank_reg(gpio, bank, reg_irq_type1);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type1;
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iowrite32(reg, addr);
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addr = bank_reg(gpio, bank, reg_irq_type2);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type2;
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iowrite32(reg, addr);
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spin_unlock_irqrestore(&gpio->lock, flags);
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irq_set_handler_locked(d, handler);
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return 0;
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}
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static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *ic = irq_desc_get_chip(desc);
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struct aspeed_sgpio *data = gpiochip_get_data(gc);
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unsigned int i, p;
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unsigned long reg;
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chained_irq_enter(ic, desc);
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
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reg = ioread32(bank_reg(data, bank, reg_irq_status));
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for_each_set_bit(p, ®, 32)
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generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
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}
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chained_irq_exit(ic, desc);
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}
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static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
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struct platform_device *pdev)
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{
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int rc, i;
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const struct aspeed_sgpio_bank *bank;
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struct gpio_irq_chip *irq;
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rc = platform_get_irq(pdev, 0);
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if (rc < 0)
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return rc;
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gpio->irq = rc;
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/* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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bank = &aspeed_sgpio_banks[i];
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/* disable irq enable bits */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
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/* clear status bits */
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iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
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}
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gpio->intc.name = dev_name(&pdev->dev);
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gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
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gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
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gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
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gpio->intc.irq_set_type = aspeed_sgpio_set_type;
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irq = &gpio->chip.irq;
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irq->chip = &gpio->intc;
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irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
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irq->handler = handle_bad_irq;
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irq->default_type = IRQ_TYPE_NONE;
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irq->parent_handler = aspeed_sgpio_irq_handler;
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irq->parent_handler_data = gpio;
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irq->parents = &gpio->irq;
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irq->num_parents = 1;
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/* Apply default IRQ settings */
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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bank = &aspeed_sgpio_banks[i];
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/* set falling or level-low irq */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
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/* trigger type is edge */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
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/* single edge trigger */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
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}
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return 0;
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}
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static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
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.pin_mask = GENMASK(9, 6),
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};
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static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
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unsigned int offset, bool enable)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
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unsigned long flags;
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void __iomem *reg;
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u32 val;
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reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
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spin_lock_irqsave(&gpio->lock, flags);
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val = readl(reg);
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if (enable)
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val |= GPIO_BIT(offset);
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else
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val &= ~GPIO_BIT(offset);
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writel(val, reg);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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}
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static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
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unsigned long config)
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{
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unsigned long param = pinconf_to_config_param(config);
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u32 arg = pinconf_to_config_argument(config);
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if (param == PIN_CONFIG_PERSIST_STATE)
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return aspeed_sgpio_reset_tolerance(chip, offset, arg);
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return -ENOTSUPP;
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}
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static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
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.pin_mask = GENMASK(10, 6),
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};
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static const struct of_device_id aspeed_sgpio_of_table[] = {
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{ .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
|
|
{ .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
|
|
{ .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
|
|
{}
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
|
|
|
|
static int __init aspeed_sgpio_probe(struct platform_device *pdev)
|
|
{
|
|
u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
|
|
const struct aspeed_sgpio_pdata *pdata;
|
|
struct aspeed_sgpio *gpio;
|
|
unsigned long apb_freq;
|
|
int rc;
|
|
|
|
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
if (!gpio)
|
|
return -ENOMEM;
|
|
|
|
gpio->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(gpio->base))
|
|
return PTR_ERR(gpio->base);
|
|
|
|
pdata = device_get_match_data(&pdev->dev);
|
|
if (!pdata)
|
|
return -EINVAL;
|
|
|
|
pin_mask = pdata->pin_mask;
|
|
|
|
rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
|
|
if (rc < 0) {
|
|
dev_err(&pdev->dev, "Could not read ngpios property\n");
|
|
return -EINVAL;
|
|
} else if (nr_gpios % 8) {
|
|
dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
|
|
nr_gpios);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
|
|
if (rc < 0) {
|
|
dev_err(&pdev->dev, "Could not read bus-frequency property\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
gpio->pclk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(gpio->pclk)) {
|
|
dev_err(&pdev->dev, "devm_clk_get failed\n");
|
|
return PTR_ERR(gpio->pclk);
|
|
}
|
|
|
|
apb_freq = clk_get_rate(gpio->pclk);
|
|
|
|
/*
|
|
* From the datasheet,
|
|
* SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
|
|
* period = 2 * (GPIO254[31:16] + 1) / PCLK
|
|
* frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
|
|
* frequency = PCLK / (2 * (GPIO254[31:16] + 1))
|
|
* frequency * 2 * (GPIO254[31:16] + 1) = PCLK
|
|
* GPIO254[31:16] = PCLK / (frequency * 2) - 1
|
|
*/
|
|
if (sgpio_freq == 0)
|
|
return -EINVAL;
|
|
|
|
sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
|
|
|
|
if (sgpio_clk_div > (1 << 16) - 1)
|
|
return -EINVAL;
|
|
|
|
gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
|
|
iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
|
|
ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
|
|
|
|
spin_lock_init(&gpio->lock);
|
|
|
|
gpio->chip.parent = &pdev->dev;
|
|
gpio->chip.ngpio = nr_gpios * 2;
|
|
gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
|
|
gpio->chip.direction_input = aspeed_sgpio_dir_in;
|
|
gpio->chip.direction_output = aspeed_sgpio_dir_out;
|
|
gpio->chip.get_direction = aspeed_sgpio_get_direction;
|
|
gpio->chip.request = NULL;
|
|
gpio->chip.free = NULL;
|
|
gpio->chip.get = aspeed_sgpio_get;
|
|
gpio->chip.set = aspeed_sgpio_set;
|
|
gpio->chip.set_config = aspeed_sgpio_set_config;
|
|
gpio->chip.label = dev_name(&pdev->dev);
|
|
gpio->chip.base = -1;
|
|
|
|
aspeed_sgpio_setup_irqs(gpio, pdev);
|
|
|
|
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver aspeed_sgpio_driver = {
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.of_match_table = aspeed_sgpio_of_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
|
|
MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
|
|
MODULE_LICENSE("GPL");
|