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The "Core Performance Boost (CPB) feature, when enabled in the BIOS, allows the OS to control the highest performance for each individual core. The active, passive and the guided modes of the amd-pstate driver do support controlling the core frequency boost when this BIOS feature is enabled. Additionally, the amd-pstate driver provides a sysfs interface allowing the user to activate/deactivate this core performance boost feature at runtime. Add support for the set_boost callback in the active mode driver to enable boost control via the cpufreq core. This ensures a consistent boost control interface across all pstate modes, including passive mode, guided mode, and active mode. With this addition, all three pstate modes can support the same boost control interface with unique interface and global CPB control. Each CPU also supports individual boost control, allowing global CPB to change all cores' boost states simultaneously. Specific CPUs can update their boost states separately, ensuring all cores' boost states are synchronized. Cc: Oleksandr Natalenko <oleksandr@natalenko.name> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Co-developed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Link: https://lore.kernel.org/r/20240626042733.3747-3-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
107 lines
3.6 KiB
C
107 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2022 Advanced Micro Devices, Inc.
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*
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* Author: Meng Li <li.meng@amd.com>
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*/
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#ifndef _LINUX_AMD_PSTATE_H
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#define _LINUX_AMD_PSTATE_H
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#include <linux/pm_qos.h>
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/*********************************************************************
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* AMD P-state INTERFACE *
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*********************************************************************/
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/**
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* struct amd_aperf_mperf
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* @aperf: actual performance frequency clock count
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* @mperf: maximum performance frequency clock count
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* @tsc: time stamp counter
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*/
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struct amd_aperf_mperf {
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u64 aperf;
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u64 mperf;
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u64 tsc;
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};
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/**
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* struct amd_cpudata - private CPU data for AMD P-State
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* @cpu: CPU number
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* @req: constraint request to apply
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* @cppc_req_cached: cached performance request hints
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* @highest_perf: the maximum performance an individual processor may reach,
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* assuming ideal conditions
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* For platforms that do not support the preferred core feature, the
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* highest_pef may be configured with 166 or 255, to avoid max frequency
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* calculated wrongly. we take the fixed value as the highest_perf.
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* @nominal_perf: the maximum sustained performance level of the processor,
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* assuming ideal operating conditions
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* @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
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* savings are achieved
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* @lowest_perf: the absolute lowest performance level of the processor
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* @prefcore_ranking: the preferred core ranking, the higher value indicates a higher
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* priority.
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* @min_limit_perf: Cached value of the performance corresponding to policy->min
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* @max_limit_perf: Cached value of the performance corresponding to policy->max
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* @min_limit_freq: Cached value of policy->min (in khz)
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* @max_limit_freq: Cached value of policy->max (in khz)
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* @max_freq: the frequency (in khz) that mapped to highest_perf
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* @min_freq: the frequency (in khz) that mapped to lowest_perf
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* @nominal_freq: the frequency (in khz) that mapped to nominal_perf
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* @lowest_nonlinear_freq: the frequency (in khz) that mapped to lowest_nonlinear_perf
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* @cur: Difference of Aperf/Mperf/tsc count between last and current sample
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* @prev: Last Aperf/Mperf/tsc count value read from register
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* @freq: current cpu frequency value (in khz)
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* @boost_supported: check whether the Processor or SBIOS supports boost mode
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* @hw_prefcore: check whether HW supports preferred core featue.
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* Only when hw_prefcore and early prefcore param are true,
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* AMD P-State driver supports preferred core featue.
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* @epp_policy: Last saved policy used to set energy-performance preference
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* @epp_cached: Cached CPPC energy-performance preference value
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* @policy: Cpufreq policy value
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* @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value
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*
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* The amd_cpudata is key private data for each CPU thread in AMD P-State, and
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* represents all the attributes and goals that AMD P-State requests at runtime.
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*/
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struct amd_cpudata {
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int cpu;
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struct freq_qos_request req[2];
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u64 cppc_req_cached;
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u32 highest_perf;
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u32 nominal_perf;
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u32 lowest_nonlinear_perf;
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u32 lowest_perf;
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u32 prefcore_ranking;
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u32 min_limit_perf;
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u32 max_limit_perf;
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u32 min_limit_freq;
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u32 max_limit_freq;
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u32 max_freq;
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u32 min_freq;
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u32 nominal_freq;
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u32 lowest_nonlinear_freq;
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struct amd_aperf_mperf cur;
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struct amd_aperf_mperf prev;
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u64 freq;
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bool boost_supported;
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bool hw_prefcore;
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/* EPP feature related attributes*/
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s16 epp_policy;
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s16 epp_cached;
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u32 policy;
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u64 cppc_cap1_cached;
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bool suspended;
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s16 epp_default;
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bool boost_state;
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};
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#endif /* _LINUX_AMD_PSTATE_H */
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