Vladimir Oltean 0b912fc93a net: dsa: felix: support changing the MTU ... Changing the MTU for this switch means altering the DEV_GMII:MAC_CFG_STATUS:MAC_MAXLEN_CFG field MAX_LEN, which in turn limits the size of frames that can be received. Special accounting needs to be done for the DSA CPU port (NPI port in hardware terms). The NPI port configuration needs to be held inside the private ocelot structure, since it is now accessed from multiple places. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2020-03-27 16:07:25 -07:00
..
arc	ARCv2: IDU-intc: Add support for edge-triggered interrupts	2019-08-26 22:34:59 +05:30
at91	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
bcm2835
brcmstb	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fsl	soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c	2019-12-09 13:54:37 -06:00
imx	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mediatek	iommu/mediatek: Clean up struct mtk_smi_iommu	2019-08-30 15:57:27 +02:00
mscc	net: dsa: felix: support changing the MTU	2020-03-27 16:07:25 -07:00
nps
qcom	soc: qcom: ocmem: add missing includes	2019-10-07 08:19:43 -07:00
rockchip	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
tegra	memory: tegra: Introduce Tegra30 EMC driver	2019-11-11 14:55:27 +01:00