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0b457dde3c
pci_update_resource() updates a hardware BAR so its address matches the kernel's struct resource UNLESS it's a disabled ROM BAR. We only update those when we enable the ROM. It's not obvious from the code why ROM BARs should be handled specially. Apparently there are Matrox devices with defective ROM BARs that read as zero when disabled. That means that if pci_enable_rom() reads the disabled BAR, sets PCI_ROM_ADDRESS_ENABLE (without re-inserting the address), and writes it back, it would enable the ROM at address zero. Add comments and references to explain why we can't make the code look more rational. The code changes are from755528c860("Ignore disabled ROM resources at setup") and8085ce084c("[PATCH] Fix PCI ROM mapping"). Link: https://lkml.org/lkml/2005/8/30/138 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
424 lines
11 KiB
C
424 lines
11 KiB
C
/*
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* drivers/pci/setup-res.c
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*
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* Extruded from code written by
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* Dave Rusling (david.rusling@reo.mts.dec.com)
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* David Mosberger (davidm@cs.arizona.edu)
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* David Miller (davem@redhat.com)
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*
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* Support routines for initializing a PCI subsystem.
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*/
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/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
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/*
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* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* Resource sorting
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/cache.h>
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#include <linux/slab.h>
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#include "pci.h"
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static void pci_std_update_resource(struct pci_dev *dev, int resno)
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{
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struct pci_bus_region region;
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bool disable;
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u16 cmd;
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u32 new, check, mask;
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int reg;
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struct resource *res = dev->resource + resno;
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/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
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if (dev->is_virtfn)
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return;
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/*
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* Ignore resources for unimplemented BARs and unused resource slots
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* for 64 bit BARs.
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*/
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if (!res->flags)
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return;
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if (res->flags & IORESOURCE_UNSET)
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return;
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/*
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* Ignore non-moveable resources. This might be legacy resources for
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* which no functional BAR register exists or another important
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* system resource we shouldn't move around.
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*/
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if (res->flags & IORESOURCE_PCI_FIXED)
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return;
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pcibios_resource_to_bus(dev->bus, ®ion, res);
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new = region.start;
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if (res->flags & IORESOURCE_IO) {
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mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
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new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
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} else if (resno == PCI_ROM_RESOURCE) {
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mask = (u32)PCI_ROM_ADDRESS_MASK;
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} else {
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mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
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new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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if (resno < PCI_ROM_RESOURCE) {
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reg = PCI_BASE_ADDRESS_0 + 4 * resno;
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} else if (resno == PCI_ROM_RESOURCE) {
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/*
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* Apparently some Matrox devices have ROM BARs that read
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* as zero when disabled, so don't update ROM BARs unless
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* they're enabled. See https://lkml.org/lkml/2005/8/30/138.
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*/
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if (!(res->flags & IORESOURCE_ROM_ENABLE))
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return;
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reg = dev->rom_base_reg;
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new |= PCI_ROM_ADDRESS_ENABLE;
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} else
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return;
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/*
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* We can't update a 64-bit BAR atomically, so when possible,
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* disable decoding so that a half-updated BAR won't conflict
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* with another device.
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*/
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disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
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if (disable) {
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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pci_write_config_word(dev, PCI_COMMAND,
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cmd & ~PCI_COMMAND_MEMORY);
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}
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pci_write_config_dword(dev, reg, new);
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pci_read_config_dword(dev, reg, &check);
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if ((new ^ check) & mask) {
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dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
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resno, new, check);
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}
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if (res->flags & IORESOURCE_MEM_64) {
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new = region.start >> 16 >> 16;
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pci_write_config_dword(dev, reg + 4, new);
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pci_read_config_dword(dev, reg + 4, &check);
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if (check != new) {
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dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
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resno, new, check);
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}
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}
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if (disable)
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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void pci_update_resource(struct pci_dev *dev, int resno)
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{
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if (resno <= PCI_ROM_RESOURCE)
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pci_std_update_resource(dev, resno);
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#ifdef CONFIG_PCI_IOV
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else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
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pci_iov_update_resource(dev, resno);
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#endif
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}
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int pci_claim_resource(struct pci_dev *dev, int resource)
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{
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struct resource *res = &dev->resource[resource];
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struct resource *root, *conflict;
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if (res->flags & IORESOURCE_UNSET) {
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dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
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resource, res);
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return -EINVAL;
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}
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root = pci_find_parent_resource(dev, res);
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if (!root) {
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dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
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resource, res);
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res->flags |= IORESOURCE_UNSET;
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return -EINVAL;
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}
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conflict = request_resource_conflict(root, res);
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if (conflict) {
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dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
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resource, res, conflict->name, conflict);
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res->flags |= IORESOURCE_UNSET;
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return -EBUSY;
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}
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return 0;
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}
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EXPORT_SYMBOL(pci_claim_resource);
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void pci_disable_bridge_window(struct pci_dev *dev)
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{
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dev_info(&dev->dev, "disabling bridge mem windows\n");
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/* MMIO Base/Limit */
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pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
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/* Prefetchable MMIO Base/Limit */
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pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
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pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
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pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
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}
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/*
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* Generic function that returns a value indicating that the device's
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* original BIOS BAR address was not saved and so is not available for
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* reinstatement.
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*
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* Can be over-ridden by architecture specific code that implements
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* reinstatement functionality rather than leaving it disabled when
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* normal allocation attempts fail.
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*/
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resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
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{
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return 0;
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}
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static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
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int resno, resource_size_t size)
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{
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struct resource *root, *conflict;
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resource_size_t fw_addr, start, end;
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fw_addr = pcibios_retrieve_fw_addr(dev, resno);
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if (!fw_addr)
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return -ENOMEM;
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start = res->start;
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end = res->end;
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res->start = fw_addr;
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res->end = res->start + size - 1;
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res->flags &= ~IORESOURCE_UNSET;
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root = pci_find_parent_resource(dev, res);
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if (!root) {
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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else
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root = &iomem_resource;
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}
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dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
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resno, res);
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conflict = request_resource_conflict(root, res);
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if (conflict) {
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dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
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resno, res, conflict->name, conflict);
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res->start = start;
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res->end = end;
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res->flags |= IORESOURCE_UNSET;
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return -EBUSY;
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}
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return 0;
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}
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static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
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int resno, resource_size_t size, resource_size_t align)
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{
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struct resource *res = dev->resource + resno;
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resource_size_t min;
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int ret;
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min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
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/*
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* First, try exact prefetching match. Even if a 64-bit
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* prefetchable bridge window is below 4GB, we can't put a 32-bit
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* prefetchable resource in it because pbus_size_mem() assumes a
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* 64-bit window will contain no 32-bit resources. If we assign
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* things differently than they were sized, not everything will fit.
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*/
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ret = pci_bus_alloc_resource(bus, res, size, align, min,
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IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
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pcibios_align_resource, dev);
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if (ret == 0)
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return 0;
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/*
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* If the prefetchable window is only 32 bits wide, we can put
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* 64-bit prefetchable resources in it.
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*/
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if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
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(IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
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ret = pci_bus_alloc_resource(bus, res, size, align, min,
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IORESOURCE_PREFETCH,
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pcibios_align_resource, dev);
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if (ret == 0)
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return 0;
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}
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/*
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* If we didn't find a better match, we can put any memory resource
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* in a non-prefetchable window. If this resource is 32 bits and
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* non-prefetchable, the first call already tried the only possibility
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* so we don't need to try again.
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*/
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if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
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ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
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pcibios_align_resource, dev);
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return ret;
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}
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static int _pci_assign_resource(struct pci_dev *dev, int resno,
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resource_size_t size, resource_size_t min_align)
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{
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struct pci_bus *bus;
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int ret;
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bus = dev->bus;
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while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
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if (!bus->parent || !bus->self->transparent)
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break;
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bus = bus->parent;
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}
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return ret;
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}
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int pci_assign_resource(struct pci_dev *dev, int resno)
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{
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struct resource *res = dev->resource + resno;
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resource_size_t align, size;
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int ret;
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if (res->flags & IORESOURCE_PCI_FIXED)
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return 0;
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res->flags |= IORESOURCE_UNSET;
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align = pci_resource_alignment(dev, res);
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if (!align) {
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dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
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resno, res);
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return -EINVAL;
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}
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size = resource_size(res);
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ret = _pci_assign_resource(dev, resno, size, align);
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/*
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* If we failed to assign anything, let's try the address
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* where firmware left it. That at least has a chance of
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* working, which is better than just leaving it disabled.
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*/
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if (ret < 0) {
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dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
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ret = pci_revert_fw_address(res, dev, resno, size);
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}
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if (ret < 0) {
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dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
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res);
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return ret;
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}
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res->flags &= ~IORESOURCE_UNSET;
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res->flags &= ~IORESOURCE_STARTALIGN;
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dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
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if (resno < PCI_BRIDGE_RESOURCES)
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pci_update_resource(dev, resno);
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return 0;
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}
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EXPORT_SYMBOL(pci_assign_resource);
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int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
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resource_size_t min_align)
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{
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struct resource *res = dev->resource + resno;
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unsigned long flags;
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resource_size_t new_size;
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int ret;
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if (res->flags & IORESOURCE_PCI_FIXED)
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return 0;
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flags = res->flags;
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res->flags |= IORESOURCE_UNSET;
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if (!res->parent) {
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dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
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resno, res);
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return -EINVAL;
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}
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/* already aligned with min_align */
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new_size = resource_size(res) + addsize;
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ret = _pci_assign_resource(dev, resno, new_size, min_align);
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if (ret) {
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res->flags = flags;
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dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
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resno, res, (unsigned long long) addsize);
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return ret;
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}
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res->flags &= ~IORESOURCE_UNSET;
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res->flags &= ~IORESOURCE_STARTALIGN;
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dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
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resno, res, (unsigned long long) addsize);
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if (resno < PCI_BRIDGE_RESOURCES)
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pci_update_resource(dev, resno);
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return 0;
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}
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int pci_enable_resources(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int i;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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if (!(mask & (1 << i)))
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continue;
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r = &dev->resource[i];
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if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
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continue;
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if ((i == PCI_ROM_RESOURCE) &&
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(!(r->flags & IORESOURCE_ROM_ENABLE)))
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continue;
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if (r->flags & IORESOURCE_UNSET) {
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dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
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i, r);
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return -EINVAL;
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}
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if (!r->parent) {
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dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
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i, r);
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
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old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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