Siarhei Volkau 07e6a6d7f1 MIPS: Take in account load hazards for HI/LO restoring ... MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load and right after move to HI/LO will usually stall the pipeline for significant amount of time. Let's take it into account and separate loads and mthi/lo in instruction sequence. The patch uses t6 and t7 registers as temporaries in addition to t8. The patch tries to deal with SmartMIPS, but I know little about and haven't tested it. Changes in v2: - clear separation of actions for SmartMIPS and pre-MIPSR6. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>		2024-05-03 14:22:38 +02:00
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asm	MIPS: Take in account load hazards for HI/LO restoring	2024-05-03 14:22:38 +02:00
uapi/asm	kvm: replace __KVM_HAVE_READONLY_MEM with Kconfig symbol	2024-02-08 08:41:06 -05:00