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06cf5583fd
- use RTC_CLASS instead of GEN_RTC - get rid of ds1216 in favour of a RTC_CLASS driver - use correct console device for older RM400 - use physical addresses for 82596 device - use 128 byte L1 cache line size (this is needed because most of the SNI caches are using 128 L2 cache lines) Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
217 lines
6.1 KiB
C
217 lines
6.1 KiB
C
/*
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* SNI specific definitions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997, 1998 by Ralf Baechle
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* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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*/
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#ifndef __ASM_SNI_H
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#define __ASM_SNI_H
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extern unsigned int sni_brd_type;
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#define SNI_BRD_10 2
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#define SNI_BRD_10NEW 3
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#define SNI_BRD_TOWER_OASIC 4
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#define SNI_BRD_MINITOWER 5
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#define SNI_BRD_PCI_TOWER 6
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#define SNI_BRD_RM200 7
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#define SNI_BRD_PCI_MTOWER 8
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#define SNI_BRD_PCI_DESKTOP 9
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#define SNI_BRD_PCI_TOWER_CPLUS 10
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#define SNI_BRD_PCI_MTOWER_CPLUS 11
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/* RM400 cpu types */
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#define SNI_CPU_M8021 0x01
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#define SNI_CPU_M8030 0x04
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#define SNI_CPU_M8031 0x06
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#define SNI_CPU_M8034 0x0f
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#define SNI_CPU_M8037 0x07
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#define SNI_CPU_M8040 0x05
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#define SNI_CPU_M8043 0x09
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#define SNI_CPU_M8050 0x0b
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#define SNI_CPU_M8053 0x0d
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#define SNI_PORT_BASE 0xb4000000
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#ifndef __MIPSEL__
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/*
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* ASIC PCI registers for big endian configuration.
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*/
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#define PCIMT_UCONF 0xbfff0004
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#define PCIMT_IOADTIMEOUT2 0xbfff000c
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#define PCIMT_IOMEMCONF 0xbfff0014
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#define PCIMT_IOMMU 0xbfff001c
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#define PCIMT_IOADTIMEOUT1 0xbfff0024
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#define PCIMT_DMAACCESS 0xbfff002c
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#define PCIMT_DMAHIT 0xbfff0034
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#define PCIMT_ERRSTATUS 0xbfff003c
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#define PCIMT_ERRADDR 0xbfff0044
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#define PCIMT_SYNDROME 0xbfff004c
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#define PCIMT_ITPEND 0xbfff0054
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#define IT_INT2 0x01
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#define IT_INTD 0x02
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#define IT_INTC 0x04
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#define IT_INTB 0x08
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#define IT_INTA 0x10
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#define IT_EISA 0x20
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#define IT_SCSI 0x40
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#define IT_ETH 0x80
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#define PCIMT_IRQSEL 0xbfff005c
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#define PCIMT_TESTMEM 0xbfff0064
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#define PCIMT_ECCREG 0xbfff006c
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#define PCIMT_CONFIG_ADDRESS 0xbfff0074
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#define PCIMT_ASIC_ID 0xbfff007c /* read */
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#define PCIMT_SOFT_RESET 0xbfff007c /* write */
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#define PCIMT_PIA_OE 0xbfff0084
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#define PCIMT_PIA_DATAOUT 0xbfff008c
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#define PCIMT_PIA_DATAIN 0xbfff0094
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#define PCIMT_CACHECONF 0xbfff009c
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#define PCIMT_INVSPACE 0xbfff00a4
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#else
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/*
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* ASIC PCI registers for little endian configuration.
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*/
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#define PCIMT_UCONF 0xbfff0000
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#define PCIMT_IOADTIMEOUT2 0xbfff0008
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#define PCIMT_IOMEMCONF 0xbfff0010
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#define PCIMT_IOMMU 0xbfff0018
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#define PCIMT_IOADTIMEOUT1 0xbfff0020
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#define PCIMT_DMAACCESS 0xbfff0028
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#define PCIMT_DMAHIT 0xbfff0030
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#define PCIMT_ERRSTATUS 0xbfff0038
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#define PCIMT_ERRADDR 0xbfff0040
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#define PCIMT_SYNDROME 0xbfff0048
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#define PCIMT_ITPEND 0xbfff0050
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#define IT_INT2 0x01
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#define IT_INTD 0x02
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#define IT_INTC 0x04
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#define IT_INTB 0x08
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#define IT_INTA 0x10
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#define IT_EISA 0x20
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#define IT_SCSI 0x40
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#define IT_ETH 0x80
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#define PCIMT_IRQSEL 0xbfff0058
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#define PCIMT_TESTMEM 0xbfff0060
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#define PCIMT_ECCREG 0xbfff0068
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#define PCIMT_CONFIG_ADDRESS 0xbfff0070
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#define PCIMT_ASIC_ID 0xbfff0078 /* read */
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#define PCIMT_SOFT_RESET 0xbfff0078 /* write */
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#define PCIMT_PIA_OE 0xbfff0080
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#define PCIMT_PIA_DATAOUT 0xbfff0088
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#define PCIMT_PIA_DATAIN 0xbfff0090
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#define PCIMT_CACHECONF 0xbfff0098
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#define PCIMT_INVSPACE 0xbfff00a0
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#endif
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#define PCIMT_PCI_CONF 0xbfff0100
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/*
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* Data port for the PCI bus in IO space
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*/
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#define PCIMT_CONFIG_DATA 0x0cfc
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/*
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* Board specific registers
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*/
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#define PCIMT_CSMSR 0xbfd00000
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#define PCIMT_CSSWITCH 0xbfd10000
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#define PCIMT_CSITPEND 0xbfd20000
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#define PCIMT_AUTO_PO_EN 0xbfd30000
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#define PCIMT_CLR_TEMP 0xbfd40000
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#define PCIMT_AUTO_PO_DIS 0xbfd50000
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#define PCIMT_EXMSR 0xbfd60000
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#define PCIMT_UNUSED1 0xbfd70000
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#define PCIMT_CSWCSM 0xbfd80000
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#define PCIMT_UNUSED2 0xbfd90000
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#define PCIMT_CSLED 0xbfda0000
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#define PCIMT_CSMAPISA 0xbfdb0000
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#define PCIMT_CSRSTBP 0xbfdc0000
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#define PCIMT_CLRPOFF 0xbfdd0000
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#define PCIMT_CSTIMER 0xbfde0000
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#define PCIMT_PWDN 0xbfdf0000
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/*
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* A20R based boards
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*/
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#define A20R_PT_CLOCK_BASE 0xbc040000
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#define A20R_PT_TIM0_ACK 0xbc050000
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#define A20R_PT_TIM1_ACK 0xbc060000
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#define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
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#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
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#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
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#define SNI_PCIT_INT_REG 0xbfff000c
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#define SNI_PCIT_INT_START 24
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#define SNI_PCIT_INT_END 30
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#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
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#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
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#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
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#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
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#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3)
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#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4)
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#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5)
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/*
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* Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
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* to the other interrupts generated by ASIC PCI.
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*
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* INT2 is a wired-or of the push button interrupt, high temperature interrupt
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* ASIC PCI interrupt.
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*/
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#define PCIMT_KEYBOARD_IRQ 1
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#define PCIMT_IRQ_INT2 24
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#define PCIMT_IRQ_INTD 25
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#define PCIMT_IRQ_INTC 26
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#define PCIMT_IRQ_INTB 27
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#define PCIMT_IRQ_INTA 28
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#define PCIMT_IRQ_EISA 29
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#define PCIMT_IRQ_SCSI 30
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#define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
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#if 0
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#define PCIMT_IRQ_TEMPERATURE 24
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#define PCIMT_IRQ_EISA_NMI 25
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#define PCIMT_IRQ_POWER_OFF 26
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#define PCIMT_IRQ_BUTTON 27
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#endif
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/*
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* Base address for the mapped 16mb EISA bus segment.
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*/
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#define PCIMT_EISA_BASE 0xb0000000
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/* PCI EISA Interrupt acknowledge */
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#define PCIMT_INT_ACKNOWLEDGE 0xba000000
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/* board specific init functions */
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extern void sni_a20r_init (void);
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extern void sni_pcit_init (void);
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extern void sni_rm200_init (void);
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extern void sni_pcimt_init (void);
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/* board specific irq init functions */
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extern void sni_a20r_irq_init (void);
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extern void sni_pcit_irq_init (void);
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extern void sni_pcit_cplus_irq_init (void);
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extern void sni_rm200_irq_init (void);
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extern void sni_pcimt_irq_init (void);
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/* timer inits */
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extern void sni_cpu_time_init(void);
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/* common irq stuff */
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extern void (*sni_hwint)(void);
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extern struct irqaction sni_isa_irq;
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#endif /* __ASM_SNI_H */
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