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0629bf17ea
Convert the swphy register generation to tabular form which allows us
to eliminate multiple switch() statements. This results in a smaller
object code size, more efficient, and easier to add support for faster
speeds.
Before:
Idx Name Size VMA LMA File off Algn
0 .text 00000164 00000000 00000000 00000034 2**2
text data bss dec hex filename
388 0 0 388 184 swphy.o
After:
Idx Name Size VMA LMA File off Algn
0 .text 000000fc 00000000 00000000 00000034 2**2
5 .rodata 00000028 00000000 00000000 00000138 2**2
text data bss dec hex filename
324 0 0 324 144 swphy.o
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
140 lines
3.2 KiB
C
140 lines
3.2 KiB
C
/*
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* Software PHY emulation
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*
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* Code taken from fixed_phy.c by Russell King <rmk+kernel@arm.linux.org.uk>
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*
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* Author: Vitaly Bordug <vbordug@ru.mvista.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* Copyright (c) 2006-2007 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/export.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include "swphy.h"
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struct swmii_regs {
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u16 bmcr;
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u16 bmsr;
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u16 lpa;
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u16 lpagb;
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};
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enum {
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SWMII_SPEED_10 = 0,
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SWMII_SPEED_100,
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SWMII_SPEED_1000,
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SWMII_DUPLEX_HALF = 0,
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SWMII_DUPLEX_FULL,
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};
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/*
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* These two tables get bitwise-anded together to produce the final result.
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* This means the speed table must contain both duplex settings, and the
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* duplex table must contain all speed settings.
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*/
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static const struct swmii_regs speed[] = {
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[SWMII_SPEED_10] = {
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.bmcr = BMCR_FULLDPLX,
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.lpa = LPA_10FULL | LPA_10HALF,
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},
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[SWMII_SPEED_100] = {
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.bmcr = BMCR_FULLDPLX | BMCR_SPEED100,
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.bmsr = BMSR_100FULL | BMSR_100HALF,
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.lpa = LPA_100FULL | LPA_100HALF,
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},
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[SWMII_SPEED_1000] = {
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.bmcr = BMCR_FULLDPLX | BMCR_SPEED1000,
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.bmsr = BMSR_ESTATEN,
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.lpagb = LPA_1000FULL | LPA_1000HALF,
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},
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};
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static const struct swmii_regs duplex[] = {
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[SWMII_DUPLEX_HALF] = {
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.bmcr = ~BMCR_FULLDPLX,
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.bmsr = BMSR_ESTATEN | BMSR_100HALF,
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.lpa = LPA_10HALF | LPA_100HALF,
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.lpagb = LPA_1000HALF,
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},
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[SWMII_DUPLEX_FULL] = {
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.bmcr = ~0,
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.bmsr = BMSR_ESTATEN | BMSR_100FULL,
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.lpa = LPA_10FULL | LPA_100FULL,
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.lpagb = LPA_1000FULL,
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},
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};
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static int swphy_decode_speed(int speed)
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{
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switch (speed) {
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case 1000:
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return SWMII_SPEED_1000;
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case 100:
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return SWMII_SPEED_100;
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case 10:
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return SWMII_SPEED_10;
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default:
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return -EINVAL;
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}
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}
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/**
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* swphy_update_regs - update MII register array with fixed phy state
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* @regs: array of 32 registers to update
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* @state: fixed phy status
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*
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* Update the array of MII registers with the fixed phy link, speed,
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* duplex and pause mode settings.
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*/
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int swphy_update_regs(u16 *regs, const struct fixed_phy_status *state)
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{
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int speed_index, duplex_index;
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u16 bmsr = BMSR_ANEGCAPABLE;
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u16 bmcr = 0;
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u16 lpagb = 0;
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u16 lpa = 0;
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speed_index = swphy_decode_speed(state->speed);
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if (speed_index < 0) {
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pr_warn("swphy: unknown speed\n");
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return -EINVAL;
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}
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duplex_index = state->duplex ? SWMII_DUPLEX_FULL : SWMII_DUPLEX_HALF;
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bmsr |= speed[speed_index].bmsr & duplex[duplex_index].bmsr;
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if (state->link) {
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bmsr |= BMSR_LSTATUS | BMSR_ANEGCOMPLETE;
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bmcr |= speed[speed_index].bmcr & duplex[duplex_index].bmcr;
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lpa |= speed[speed_index].lpa & duplex[duplex_index].lpa;
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lpagb |= speed[speed_index].lpagb & duplex[duplex_index].lpagb;
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if (state->pause)
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lpa |= LPA_PAUSE_CAP;
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if (state->asym_pause)
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lpa |= LPA_PAUSE_ASYM;
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}
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regs[MII_PHYSID1] = 0;
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regs[MII_PHYSID2] = 0;
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regs[MII_BMSR] = bmsr;
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regs[MII_BMCR] = bmcr;
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regs[MII_LPA] = lpa;
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regs[MII_STAT1000] = lpagb;
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return 0;
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}
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EXPORT_SYMBOL_GPL(swphy_update_regs);
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